Processor Types and Performance (overview)

CSS Optional — Paper-II, Section-A · Chapter 7

This page gives the compact overview of processor design philosophy and performance measurement. For deep treatment with more solved numericals, see the dedicated CISC vs RISC and Performance Metrics pages.

1. Definition

• CISC (Complex Instruction Set Computer) — a design philosophy using many specialised, multi-step instructions of variable length, minimising the number of instructions per program.
• RISC (Reduced Instruction Set Computer) — a design philosophy using a small set of simple, fixed-length, single-cycle instructions, relying on compiler optimisation and pipelining.

2. Classification — CISC vs RISC (summary)

3. Classification — Performance Metrics

• Clock speed — cycles per second (Hz); how fast the clock ticks.
• CPI (Cycles Per Instruction) — average hardware cycles consumed per instruction.
• MIPS (Million Instructions Per Second) — instruction throughput; unreliable across different ISAs.
• Throughput — completed tasks per unit time.

4. Key Formulas — Processor Performance

4.1 CPU Execution Time (the master equation)

$$T = IC \times CPI \times T_{c}$$ $$T = \frac{IC \times CPI}{f} = \frac{\text{Total clock cycles}}{f}$$

• $IC$ = instruction count
• $CPI$ = average cycles per instruction
• $T_c$ = clock cycle time, $f$ = clock rate

4.2 Clock Rate and Cycle Time

$$T_{c} = \frac{1}{f} \qquad f = \frac{1}{T_{c}}$$

• 1 GHz means a cycle time of 1 ns
• 2 GHz means a cycle time of 0.5 ns
• 4 GHz means a cycle time of 0.25 ns

4.3 Total Clock Cycles

$$\text{Total cycles} = IC \times CPI$$ $$\text{Total cycles} = T \times f$$

4.4 CPI

$$CPI = \frac{\text{Total clock cycles}}{IC}$$ $$CPI = \frac{T \times f}{IC}$$

• Weighted CPI using counts:

$$CPI_{avg} = \frac{\sum (CPI_i \times Count_i)}{\sum Count_i}$$

• Weighted CPI using fractions:

$$CPI_{avg} = \sum (CPI_i \times F_i), \quad \sum F_i = 1$$

4.5 IPC (inverse of CPI)

$$IPC = \frac{1}{CPI} \qquad CPI = \frac{1}{IPC}$$

4.6 Effective CPI with Stalls

$$CPI_{eff} = CPI_{base} + \text{Memory stalls} + \text{Branch stalls}$$ $$\text{Memory stalls} = \text{Accesses per instruction} \times \text{Miss rate} \times \text{Miss penalty}$$ $$\text{Branch stalls} = \text{Branch frequency} \times \text{Misprediction rate} \times \text{Penalty}$$

4.7 MIPS

$$MIPS = \frac{IC}{T \times 10^{6}}$$ $$MIPS = \frac{f}{CPI \times 10^{6}}$$

4.8 Speedup and Comparing Machines

$$\text{Speedup} = \frac{T_{old}}{T_{new}}$$ $$\text{Speedup} = \frac{CPI_{old} \times T_{c,old}}{CPI_{new} \times T_{c,new}} \quad (IC \text{ unchanged})$$

4.9 Amdahl's Law

$$\text{Speedup} = \frac{1}{(1 - P) + \frac{P}{S}}$$ $$\text{Max Speedup} = \frac{1}{1 - P}$$

• $P$ = fraction of time that can be improved
• $S$ = speedup applied to that fraction

4.10 Parallel Speedup and Efficiency

$$S_p = \frac{T_{1}}{T_{N}} \qquad E = \frac{S_p}{N}$$

4.11 Pipeline Performance

$$T_{\text{no pipeline}} = n \times k \times T_{c}$$ $$T_{\text{pipeline}} = (k + n - 1) \times T_{c}$$ $$\text{Speedup} = \frac{n \times k}{k + n - 1} \;\longrightarrow\; k \quad (n \to \infty)$$

• $n$ = number of instructions, $k$ = number of pipeline stages

4.12 Throughput and Power

$$\text{Throughput} = \frac{\text{Tasks completed}}{\text{Time}}$$ $$P_{dynamic} = C \times V^{2} \times f$$

• Power rises with frequency, and with the square of voltage, which is why clock speed hit a limit (the power wall)

🗺️ Architecture Diagram — What Determines Performance

graph LR
    ISA["ISA Design
RISC vs CISC"] --> IC["Instruction Count"]
    ISA --> CPI["CPI"]
    TECH["Hardware Technology"] --> CT["Clock Cycle Time"]
    IC --> T["Execution Time
T = IC x CPI x Cycle Time"]
    CPI --> T
    CT --> T

🧮 Solved Numerical — Execution Time

Q: A processor executes 5,000 instructions with an average CPI of 3, at a clock rate of 2 GHz. Find the execution time.

Given: $IC = 5{,}000$, $CPI = 3$, $f = 2\ \text{GHz}$

Solution:

$$\begin{aligned} T_c &= \frac{1}{2\ \text{GHz}} = 0.5\ \text{ns} \\ T &= IC \times CPI \times T_c \\ &= 5{,}000 \times 3 \times 0.5\ \text{ns} \\ &= 7{,}500\ \text{ns} = 7.5\ \mu\text{s} \end{aligned}$$

Answer: 7.5 μs.

🎯 CSS Exam Angle

RISC vs CISC is one of the most repeated CS-optional questions across multiple years — treat it as near-guaranteed.

🔁 Repeated CSS Questions

1. Differentiate between RISC and CISC processors. (Very frequently repeated)
2. Define CPI and MIPS. How are they related to processor performance?
3. Calculate execution time given instruction count, CPI, and clock rate. (Numerical)

⚠️ MCQ Trap

RISC = simple, fixed-length instructions, relies on compiler/pipelining; CISC = complex, variable-length instructions, does more per instruction.