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Multi-Processor and Multi-core Systems

CSS Optional — Paper-II, Computer Organization & Architecture

1. Definition

A multiprocessor system contains two or more independent CPUs (traditionally on separate chips/packages) within a single computer system, coordinated to execute programs together. A multicore system integrates two or more independent processing cores onto a single chip/package, sharing some on-chip resources (e.g., the last-level cache and memory controller) that separate-chip multiprocessors do not share.

⚠️ MCQ favourite: multicore = multiple cores on one chip; multiprocessor = multiple separate CPU chips in one system. The two terms are often loosely conflated in casual speech but are a precise, frequently tested distinction in this paper.

2. Classification — Multiprocessor Organization

  • Symmetric Multiprocessing (SMP) — all processors are identical, share a single main memory equally, and run under a single operating system image with equal access to all I/O; the standard organisation for most modern servers and multicore chips.
  • Asymmetric Multiprocessing (AMP) — processors are assigned specialised, unequal roles (e.g., one master processor handles OS/scheduling, others are dedicated workers) — simpler to implement than SMP but less flexible and less scalable.
  • NUMA (Non-Uniform Memory Access) — each processor (or cluster of processors) has memory physically local to it, which it accesses faster than memory local to a different processor; used to scale shared-memory systems beyond what a single shared bus can support (see Numerical 2 below).
  • MPP (Massively Parallel Processing) — a large number of independent nodes, each with its own processor and memory, connected by a high-speed interconnect and communicating via message passing rather than shared memory — the distributed-memory extreme, used in supercomputers.

3. Classification — Multicore Design Choices

  • Homogeneous multicore — all cores are identical in architecture and performance (the common case: e.g., 4 identical cores).
  • Heterogeneous multicore — cores differ in capability (e.g., ARM's big.LITTLE: a few high-performance cores paired with several power-efficient cores for the same instruction set, chosen per task by the scheduler).
  • Cache sharing — typically each core has a private L1/L2 cache, while the L3 cache is shared across all cores on the chip — the shared L3 doubles as the medium through which cores exchange data quickly without going to main memory.

4. The Cache Coherence Problem ⭐

When multiple cores each cache their own private copy of the same memory location, one core's write can leave other cores holding a stale copy — this is the cache coherence problem, unique to multiprocessor/multicore systems (a single-core system never faces it).

  • Snooping protocols — every cache "listens" (snoops) on a shared bus for writes to addresses it holds a copy of, and invalidates or updates its own copy accordingly. Practical mainly on bus-based systems with a modest core count, since every core must observe every transaction.
  • MESI protocol — the standard snooping-based coherence protocol, naming each cache line's state:
    • M (Modified) — dirty, present only in this cache; must write back before another core can read it.
    • E (Exclusive) — clean, present only in this cache; can be silently upgraded to Modified without a bus transaction.
    • S (Shared) — clean, potentially present in multiple caches.
    • I (Invalid) — this cache's copy is stale/unusable.
  • Directory-based protocols — used in NUMA/large-scale systems instead of snooping, since broadcasting to every cache does not scale; a central (or distributed) directory tracks exactly which caches hold which line, so coherence traffic is sent only to the caches that actually need it.

5. Interconnection Networks (how the processors actually talk)

  • Bus-based — simple, cheap, but a single shared resource that saturates as core count grows (see Numerical 2).
  • Crossbar switch — any processor can reach any memory module directly without contention with unrelated pairs, at the cost of O(n²) switching hardware — fast but expensive to scale.
  • Mesh / Ring / Hypercube topologies — used in large multiprocessor/MPP systems to give good scalability with more modest hardware cost than a full crossbar, at the price of variable (non-uniform) latency between distant nodes.

🧮 Solved Numerical 1 — Amdahl's Law for a Multicore Upgrade

Q: A program is 90% parallelizable. Find the speedup achievable on an 8-core processor.

p = 0.9, N = 8

S = 1 / [(1 − 0.9) + (0.9 / 8)]
  = 1 / [0.1 + 0.1125]
  = 1 / 0.2125
  ≈ 4.71

Answer: ≈4.71× speedup on 8 cores — barely over half of the "ideal" 8×, a direct illustration of why simply adding cores gives sharply diminishing returns once the serial fraction dominates.

🧮 Solved Numerical 2 — Bus Saturation in an SMP System

Q: Each processor core generates 500 MB/s of memory traffic. The shared system bus has a bandwidth of 2 GB/s. What is the maximum number of cores this bus-based SMP design can support before the bus saturates?

N_max = Bus bandwidth / Traffic per core
      = 2,000 MB/s / 500 MB/s
      = 4 cores

Answer: 4 cores — beyond this point, the shared bus becomes the system bottleneck regardless of how many additional cores are added, which is exactly why systems scaling past a handful of cores move to NUMA or a crossbar/mesh interconnect instead of a single shared bus.

🧮 Solved Numerical 3 — NUMA Local vs Remote Access Penalty

Q: In a NUMA system, a local memory access takes 60 ns and a remote (cross-node) access takes 180 ns. A program makes 70% local and 30% remote memory accesses. Find the average memory access time.

T_avg = (0.70 × 60) + (0.30 × 180)
      = 42 + 54
      = 96 ns

Answer: 96 ns average — versus a hypothetical uniform-access system at 60 ns, showing concretely why NUMA-aware scheduling (keeping a process's memory local to the core running it) matters for performance.

🎯 CSS Exam Angle

  • The multiprocessor vs multicore distinction, and SMP vs AMP vs NUMA, are near-guaranteed short questions — a labelled comparison table earns quick, reliable marks.
  • Cache coherence and MESI is the conceptual centrepiece of this topic; be ready to explain why the problem exists (private per-core caches of shared data) before describing the protocol that solves it.
  • Pair this topic with Amdahl's Law (from the Parallel Processing page) whenever a question asks about the practical benefit of adding more cores — examiners like to see the numerical link between the two topics.

🔁 Repeated CSS Questions

  1. Differentiate between a multiprocessor system and a multicore system.
  2. Differentiate between symmetric and asymmetric multiprocessing.
  3. What is the cache coherence problem, and how does the MESI protocol solve it?
  4. Explain NUMA and why it is used instead of a uniform shared-bus design at scale.
  5. Calculate the speedup achievable on a multicore system for a given parallelizable fraction. (Numerical)
  6. Compare bus-based, crossbar, and mesh interconnection networks for multiprocessor systems.

⚠️ MCQ Traps

  • Multicore = one chip, multiple cores; multiprocessor = multiple chips, one system. The most commonly tested distinction on this page.
  • Cache coherence is a problem unique to systems with multiple private caches of shared data — a single-core, single-cache system never needs a coherence protocol.
  • Snooping protocols do not scale well past a modest number of cores because every cache must observe every bus transaction; directory-based protocols exist specifically to fix this.
  • NUMA access time is non-uniform by design — local and remote accesses genuinely take different amounts of time; this is not a flaw to be "fixed," it's the trade-off that lets the system scale past a single shared bus.
  • A shared bus is the classic SMP scalability bottleneck — this is why large systems move to NUMA, crossbars, or mesh interconnects.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2024 · Paper-II · Q2(a) · 7 marks

Q. Why are multi-processor systems considered advantageous in computer architecture? How does parallel processing fundamentally improve performance and scalability?

Ans.

  • Advantages of multiprocessor systems:
    • higher throughput: several programs or threads run at once
    • reliability: if one processor fails, the others continue (graceful degradation)
    • scalability: capacity grows by adding processors
    • cost effectiveness: shared memory, disks and power supplies are cheaper than several separate computers
  • How parallel processing improves performance: the work is divided among processors that run at the same time, so a task of time T on N processors can ideally take T / N.
  • Amdahl's law: speed-up = 1 / ((1 − P) + P / N), where P is the parallel fraction. If P = 0.9 and N = 8, the speed-up is 1 / (0.1 + 0.1125) ≈ 4.7. The serial part limits the gain.
  • Scalability limits: memory bandwidth, cache coherence traffic and communication overhead.
  • Types: SMP (shared memory), clusters, and multi-core chips.