Computer Function and Interconnections

CSS Optional — Paper-II, Computer Organization & Architecture

1. Definition

System interconnection is the set of pathways (buses) and techniques by which the CPU, memory, and I/O devices exchange data and control information to carry out a computer's function.

2. Classification — The Three System Buses

• Data bus — carries the actual data being transferred; bidirectional.
• Address bus — carries the memory or I/O address being accessed; unidirectional, driven by the CPU.
• Control bus — carries control and timing signals (read/write, clock, interrupts); bidirectional.

3. Classification — I/O Techniques

• Programmed I/O — the CPU actively polls device status in a loop; simple, but wastes CPU cycles.
• Interrupt-driven I/O — the device signals the CPU only when ready; more efficient for infrequent events.
• DMA (Direct Memory Access) — data transfers directly between device and memory, bypassing the CPU almost entirely; most efficient for large/bulk transfers.

🗺️ Architecture Diagram — System Interconnection

graph LR
    CPU["CPU"] <--> DBUS["Data Bus"]
    CPU --> ABUS["Address Bus"]
    CPU <--> CBUS["Control Bus"]
    DBUS <--> MEM["Main Memory"]
    ABUS --> MEM
    CBUS --> MEM
    DBUS <--> IO["I/O Devices"]
    ABUS --> IO
    CBUS --> IO

🎯 CSS Exam Angle

The bus-structure diagram (data/address/control) and the I/O technique comparison are both near-guaranteed short questions. For deeper bus bandwidth/addressable-memory numericals, see the dedicated BUS page; for interrupt classification, see I/O Types.

🔁 Repeated CSS Questions

1. Explain the three types of system bus with a labeled diagram.
2. Compare programmed I/O, interrupt-driven I/O, and DMA.
3. Why is DMA considered the most efficient I/O technique for bulk transfers?

⚠️ MCQ Trap

DMA bypasses the CPU for the bulk of data transfer, making it more efficient than programmed or interrupt-driven I/O for large transfers — but it still needs the CPU briefly to set up the transfer.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2017 · Paper-II · Q5(a) and 2018 · Paper-II · Q2(A) · 8 marks each

Q. Explain the functionality and purposes of the registers MAR, MBR (MDR), IR and PC, with diagrams.

Ans.

• MAR (Memory Address Register): holds the address of the memory location to be read or written. It is connected to the address bus.
• MBR / MDR (Memory Buffer or Data Register): holds the data just read from memory or about to be written. It is connected to the data bus.
• IR (Instruction Register): holds the instruction currently being executed. Its opcode goes to the control unit for decoding.
• PC (Program Counter): holds the address of the next instruction. It is incremented after each fetch, and branches load a new value.

CPU                                         Memory
PC ──→ MAR ═══ address bus ═══════════→  [ address ]
IR ←── MBR ═══ data bus (two-way) ═════ [  data   ]
 │
 └──→ Control unit ═══ control bus ═══→ read / write

• Fetch sequence: MAR ← PC; issue Memory Read; MDR ← Memory[MAR]; IR ← MDR; update PC to the next instruction address (often PC + instruction length).
• Eight-mark explanation: (i) PC holds the next instruction address; (ii) MAR sends that address on the address bus; (iii) the control unit asserts Memory Read; (iv) MDR receives the fetched instruction via the data bus; (v) IR holds it for decode; (vi) PC advances or is changed by a branch. The four register definitions, labeled diagram and stepwise fetch explanation together provide an appropriately developed answer.