Instruction Execution Cycle

CSS Optional — Paper-II, Section-A · Chapter 7

1. Definition

The instruction execution cycle (machine cycle) is the repeating sequence of steps the CPU performs to fetch an instruction from memory, interpret it, and carry it out — repeated once for every instruction in a program.

2. Classification — The Stages

• Fetch — the instruction at the address in the Program Counter (PC) is retrieved from memory into the Instruction Register (IR); the PC is then incremented to point at the next instruction.
• Decode — the Control Unit interprets the opcode and operand fields of the IR.
• Execute — the ALU (or relevant unit) carries out the operation.
• Store / Writeback — the result, if any, is written back to a register or memory.
• Interrupt cycle (optional fifth stage) — after execute, the CPU checks for pending interrupts and services them before fetching the next instruction.

🗺️ Architecture Diagram — Fetch-Decode-Execute Cycle

graph LR
    F["Fetch
PC to MAR, Mem to MBR to IR
PC = PC + 1"] --> D["Decode
CU interprets opcode in IR"]
    D --> E["Execute
ALU acts"]
    E --> S["Store
Write result back"]
    S --> I{"Interrupt pending?"}
    I -->|Yes| ISR["Service Interrupt"]
    I -->|No| F
    ISR --> F

3. Register Roles at Each Stage

⏱️ Timing Formulas for the Instruction Cycle

Notation: $f$ = clock rate, $T_c$ = clock cycle time, $t_{mem}$ = memory access time, $N$ = number of instructions, $k$ = number of pipeline stages.

1. Clock cycle time

$$T_c = \frac{1}{f}$$

2. Time of one instruction (no pipelining)

When the stages are given in clock cycles, add them:

$$C_{instr} = C_{fetch} + C_{decode} + C_{operand} + C_{execute} + C_{store}$$ $$T_{instr} = C_{instr} \times T_c$$

When the stages are given in ns, add the times directly:

$$T_{instr} = T_{fetch} + T_{decode} + T_{operand} + T_{execute} + T_{store}$$

3. When memory accesses decide the time

The fetch needs 1 memory access, and each operand read or result write needs one more (indirect addressing needs 2 reads):

$$T_{instr} = (1 + n_{read} + n_{write}) \times t_{mem} + T_{decode} + T_{execute}$$

Here $n_{read}$ is the number of memory reads for operands and $n_{write}$ is the number of memory writes for the result (0 if the result stays in a register).

4. Time for a whole program

$$\text{Total cycles} = N \times C_{instr} \qquad T_{prog} = N \times T_{instr} = \frac{N \times C_{instr}}{f}$$

5. Mixed instruction types

$$C_{avg} = \sum (F_i \times C_i) \qquad \text{where } \sum F_i = 1$$

$C_{avg}$ is the same quantity as CPI, so $T_{prog} = N \times C_{avg} \times T_c$.

6. Instruction rate

$$MIPS = \frac{f}{C_{avg} \times 10^{6}} = \frac{1}{T_{instr} \times 10^{6}}$$

7. Effect of interrupts

If an interrupt occurs with probability $p$ per instruction and its service routine takes $C_{int}$ cycles:

$$C_{eff} = C_{instr} + p \times C_{int}$$

8. Machine cycles and T-states (microprocessor style)

One T-state is one clock period. A machine cycle (opcode fetch, memory read, memory write, I/O) takes several T-states, and an instruction takes one or more machine cycles:

$$T_{instr} = (\text{total T-states}) \times T_c$$

9. With pipelining

For $k$ stages, $n$ instructions and stage time $t_p$ (the longest stage delay, plus latch delay):

$$T_{seq} = n \times (\text{sum of the stage times}) \qquad T_{pipe} = (k + n - 1) \times t_p$$ $$\text{Speed-up} = \frac{T_{seq}}{T_{pipe}} \qquad \text{Efficiency} = \frac{\text{Speed-up}}{k} \qquad \text{Throughput} = \frac{n}{T_{pipe}}$$

When $n$ is very large, the speed-up approaches $k$. The slowest stage sets the speed of the whole pipeline, so unbalanced stages waste time (Numerical 4).

🧮 Solved Numerical 1 — Cycles for a Program

Q: Fetch takes 2 cycles, Decode takes 1 cycle, and Execute takes 3 cycles. A program has 100 instructions with no pipelining. Find the total cycles.

Given: $C_{fetch} = 2$, $C_{decode} = 1$, $C_{execute} = 3$, $N = 100$, no pipelining.

Step 1 — Cycles per instruction:

$$C_{instr} = 2 + 1 + 3 = 6$$

Step 2 — Total cycles:

$$\text{Total cycles} = N \times C_{instr} = 100 \times 6 = 600$$

Answer: 600 cycles.

Extension — time on a 2 GHz clock:

$$\begin{aligned} T_c &= \frac{1}{2 \times 10^{9}} = 0.5\ \text{ns} \\ T_{prog} &= 600 \times 0.5\ \text{ns} = 300\ \text{ns} \end{aligned}$$

🧮 Solved Numerical 2 — Instruction Time from Memory Accesses

Q: A memory access takes 100 ns, decode takes 20 ns and execute takes 30 ns. The instruction ADD 500 reads one operand from memory and keeps the result in the accumulator. Find its time and MIPS rate, and compare it with the indirect form ADD (500). How long do 1,000 direct instructions take?

Step 1 — Direct addressing ($n_{read} = 1$, $n_{write} = 0$):

$$\begin{aligned} T_{direct} &= (1 + 1 + 0) \times 100 + 20 + 30 \\ &= 200 + 50 = 250\ \text{ns} \end{aligned}$$

Step 2 — Indirect addressing ($n_{read} = 2$):

$$\begin{aligned} T_{indirect} &= (1 + 2 + 0) \times 100 + 20 + 30 \\ &= 300 + 50 = 350\ \text{ns} \end{aligned}$$

Step 3 — MIPS and comparison:

$$\begin{aligned} MIPS_{direct} &= \frac{1}{250 \times 10^{-9} \times 10^{6}} = \frac{1}{0.25} = 4 \\ MIPS_{indirect} &= \frac{1}{0.35} = 2.86 \\ \frac{T_{indirect}}{T_{direct}} &= \frac{350}{250} = 1.4 \end{aligned}$$

Step 4 — Program of 1,000 direct instructions:

$$T_{prog} = 1{,}000 \times 250\ \text{ns} = 250{,}000\ \text{ns} = 250\ \mu\text{s}$$

Answer: 250 ns (4 MIPS) for direct, 350 ns (2.86 MIPS) for indirect, and 250 μs for the program. The one extra memory access makes the indirect form 1.4 times slower.

🧮 Solved Numerical 3 — Cost of Interrupts

Q: An instruction takes 6 cycles. An interrupt occurs once in every 100 instructions and its service routine takes 120 cycles. Find the effective cycles per instruction, the overhead, and the time for 100 instructions on a 1 GHz clock.

Given: $C_{instr} = 6$, $p = \frac{1}{100} = 0.01$, $C_{int} = 120$.

$$\begin{aligned} C_{eff} &= C_{instr} + p \times C_{int} \\ &= 6 + 0.01 \times 120 = 6 + 1.2 = 7.2 \\ \text{Overhead} &= \frac{1.2}{6} = 0.20 = 20\% \\ \text{Cycles for 100 instructions} &= 100 \times 7.2 = 720 \\ T &= 720 \times 1\ \text{ns} = 720\ \text{ns} \end{aligned}$$

Answer: 7.2 cycles per instruction, a 20% overhead, and 720 ns.

🧮 Solved Numerical 4 — Pipelined against Sequential Time

Q: Use the stages of Numerical 1 (fetch 2 cycles, decode 1 cycle, execute 3 cycles) and 100 instructions. Find the pipelined time, speed-up and efficiency. What would they be if the stages were balanced?

Step 1 — Sequential time:

$$T_{seq} = 100 \times (2 + 1 + 3) = 600\ \text{cycles}$$

Step 2 — Pipelined time. The stage time is set by the slowest stage, $t_p = \max(2, 1, 3) = 3$ cycles, and $k = 3$:

$$T_{pipe} = (k + n - 1) \times t_p = (3 + 100 - 1) \times 3 = 102 \times 3 = 306\ \text{cycles}$$

Step 3 — Speed-up and efficiency:

$$\text{Speed-up} = \frac{600}{306} = 1.96 \qquad \text{Efficiency} = \frac{1.96}{3} = 0.65 = 65\%$$

Step 4 — Balanced stages (6 cycles shared equally gives $t_p = \frac{6}{3} = 2$):

$$\begin{aligned} T_{pipe} &= 102 \times 2 = 204\ \text{cycles} \\ \text{Speed-up} &= \frac{600}{204} = 2.94 \qquad \text{Efficiency} = \frac{2.94}{3} = 98\% \end{aligned}$$

Answer: 306 cycles, speed-up 1.96, efficiency 65%. With balanced stages: 204 cycles, speed-up 2.94, efficiency 98%. The slow execute stage holds back the whole pipeline.

🧮 Solved Numerical 5 — Mixed Instruction Types

Q: A 2 GHz processor runs these instructions: ALU 40% (5 cycles), load 30% (8 cycles), store 10% (7 cycles), branch 20% (6 cycles). Find the average cycles per instruction, the time per instruction, the MIPS rate, and the time for 10,000 instructions.

Step 1 — Check the fractions: $0.40 + 0.30 + 0.10 + 0.20 = 1.00$.

Step 2 — Average cycles:

$$\begin{aligned} C_{avg} &= (0.40 \times 5) + (0.30 \times 8) + (0.10 \times 7) + (0.20 \times 6) \\ &= 2.0 + 2.4 + 0.7 + 1.2 = 6.3 \end{aligned}$$

Step 3 — Time per instruction and MIPS:

$$\begin{aligned} T_c &= \frac{1}{2 \times 10^{9}} = 0.5\ \text{ns} \\ T_{instr} &= 6.3 \times 0.5 = 3.15\ \text{ns} \\ MIPS &= \frac{2 \times 10^{9}}{6.3 \times 10^{6}} = 317.5 \end{aligned}$$

Step 4 — Program time:

$$\begin{aligned} \text{Total cycles} &= 10{,}000 \times 6.3 = 63{,}000 \\ T_{prog} &= 63{,}000 \times 0.5\ \text{ns} = 31{,}500\ \text{ns} = 31.5\ \mu\text{s} \end{aligned}$$

Answer: 6.3 cycles, 3.15 ns, about 317.5 MIPS, and 31.5 μs.

🎯 CSS Exam Angle

A reliable diagram-based question — examiners want the Fetch-Decode-Execute cycle drawn and explained with the role of PC/IR/MAR/MBR at each stage.

For a numerical, write the formula first and then substitute. Check whether the question wants cycles or time, whether the stage times are in cycles or ns, and whether pipelining is allowed. Give the unit with the final answer.

🔁 Repeated CSS Questions

1. Explain the Fetch-Decode-Execute cycle with a diagram. (Frequently repeated)
2. What role do the PC, IR, MAR, and MBR play during instruction execution?
3. How does pipelining improve on the basic sequential instruction cycle?

⚠️ MCQ Trap

The Program Counter is updated to point to the NEXT instruction during the Fetch stage — before the current instruction even finishes executing.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2016 · Paper-II · Q3(b), 2017 · Paper-II · Q2(c), 2024 · Paper-II · Q3(c) · 6 marks each

Combined revision prompt (three related past-paper questions): (i) Elaborate the basic instruction cycle with a diagram; (ii) draw and explain the instruction execution state diagram with interrupts; (iii) break down the instruction-cycle stages and relate their implementation to CISC and RISC. Exam instruction: These are distinct 6-mark prompts: select only the relevant parts of the model answer, rather than reproducing every subsection for each question.

Ans.

• Instruction cycle: the processor repeats this for every instruction.

Fetch ──→ Decode ──→ Execute ──→ (Store result) ──→ Interrupt check ──┐
  ↑                                                                   │
  └───────────── no interrupt pending ────────────────────────────────┘
                 interrupt pending → save PC, jump to the interrupt handler, then return

• Detailed states: instruction address calculation → instruction fetch → instruction operation decoding → operand address calculation → operand fetch → data operation (execute) → operand address calculation → operand store. Multiple operands or results repeat the operand states.
• Registers used: PC holds the next instruction address, MAR holds the address sent to memory, MBR holds the data returned, IR holds the instruction being decoded.
• Interrupt in the cycle: after each instruction the processor checks for a pending interrupt. If one exists and is enabled, it saves the PC and status, loads the address of the interrupt service routine, runs it, then resumes the original program.
• Effect of CISC and RISC: RISC instructions have fixed length and a regular format, so the decode stage is simple and every instruction takes about one clock in a pipeline. CISC instructions vary in length and complexity, need multi-cycle (often microprogrammed) execution and have complex operand addressing, so cycles per instruction vary widely.