optional · CSS study notes
Processor Types
CSS Optional — Paper-II, Section-A · Chapter 7
The textbook lists "Processor Types" as a topic distinct from CPU Architecture. Here the focus is on classifying processors by purpose, word size, and design philosophy, not on internal register structure (see CPU Architecture for that).
🗺️ Architecture Diagram — Processor Classification
graph TD
P["Processors"] --> GPP["General Purpose
Core i7, Ryzen"]
P --> MCU["Microcontroller
ATmega328, Cortex-M"]
P --> DSP["DSP
MAC unit, Harvard"]
P --> GPU["GPU
SIMD, 1000s of cores"]
P --> ASIC["ASIC
fixed function"]
P --> FPGA["FPGA
reconfigurable logic"]
1. Classification by Purpose
- General-Purpose Processor (GPP) — the CPU in a desktop, laptop, or server. Designed to run any program reasonably well rather than one program excellently. Examples: Intel Core i7, AMD Ryzen, Apple M-series.
- Microcontroller (MCU) — an entire small computer on one chip: CPU core + RAM + ROM/Flash + I/O ports + timers. Used in washing machines, cars, IoT devices. Examples: Arduino's ATmega328, ARM Cortex-M.
- Digital Signal Processor (DSP) — optimized for repetitive maths on continuous data streams (audio, video, radar). Its defining feature is a hardware MAC (Multiply-Accumulate) unit that performs
a = a + (b × c)in a single cycle, plus Harvard architecture for parallel instruction/data fetch. - Graphics Processing Unit (GPU) — thousands of simple cores executing the same instruction across huge data sets. Classified as SIMD in Flynn's taxonomy. Now the workhorse of AI/ML training.
- ASIC (Application-Specific Integrated Circuit) — hardwired for exactly one task (e.g., a Bitcoin mining chip). Fastest and most power-efficient, but cannot be reprogrammed.
- FPGA (Field-Programmable Gate Array) — hardware whose logic gates can be rewired after manufacture. Sits between GPP flexibility and ASIC speed.
Comparison Table (high-yield)
| Processor | Flexibility | Speed for its task | Power efficiency | Typical use |
|---|---|---|---|---|
| GPP | Highest | Moderate | Low | PCs, servers |
| GPU | Moderate | Very high (parallel) | Moderate | Graphics, AI |
| DSP | Moderate | High (signal maths) | Good | Audio, telecom |
| Microcontroller | Moderate | Low | Excellent | Embedded devices |
| FPGA | Reconfigurable | High | Good | Prototyping |
| ASIC | None (fixed) | Highest | Highest | Crypto mining |
2. Classification by Word Size
The word size is the number of bits the CPU processes in one operation and typically the width of its registers.
- 8-bit / 16-bit — legacy and embedded systems.
- 32-bit — can address 2³² bytes = 4 GB of RAM. This is the hard reason 32-bit Windows could never use more than ~4 GB.
- 64-bit — can theoretically address 2⁶⁴ bytes = 16 exabytes. All modern desktop CPUs are 64-bit.
3. Classification by Design Philosophy
Briefly: RISC (simple fixed-length instructions, hardwired control, many registers) versus CISC (complex variable-length instructions, microprogrammed control). This comparison is examined so often it has its own page — see CISC vs RISC.
4. Multicore and Hyper-threading
- Multicore: several complete processor cores on one physical chip, each able to execute an independent instruction stream (MIMD).
- Hyper-threading / SMT (Simultaneous Multithreading): one physical core presents itself to the OS as two logical cores by duplicating the register set but sharing the execution units. It fills idle cycles rather than doubling raw power — a 4-core hyper-threaded CPU shows 8 logical cores but delivers roughly 4.3–5 cores' worth of real throughput.
🧮 Solved Numerical 1 — Addressable Memory by Word Size
Q: A 32-bit processor has a 32-bit address bus. What is the maximum RAM it can address, and why did 32-bit operating systems cap out at 4 GB?
Addressable locations = 2ⁿ where n = address bus width
= 2³² = 4,294,967,296 bytes
= 4,294,967,296 / (1024×1024×1024) GB
= 4 GB
Answer: 4 GB. Each address points to one byte, so with only 32 address lines there are no bit patterns left to name a 4,294,967,297th byte. The limit is architectural, not a software choice.
🧮 Solved Numerical 2 — Effective Cores with Hyper-threading
Q: A 6-core CPU with hyper-threading gives roughly 25% extra throughput per core from SMT. How many "effective cores" of work does it deliver, and how many logical cores does the OS report?
Logical cores reported = 6 physical × 2 threads = 12 logical cores
Effective throughput = 6 × 1.25 = 7.5 effective cores
Answer: OS reports 12 logical cores, but real throughput ≈ 7.5 cores. This gap is exactly why hyper-threading must never be described as "doubling performance."
🧮 Solved Numerical 3 — Choosing a Processor Type
Q: A telecom company must filter 48,000 audio samples per second, applying a 20-tap filter (20 multiply-accumulate operations per sample). How many MAC operations per second are required, and which processor type is best suited?
MAC operations/sec = 48,000 samples × 20 taps
= 960,000 MAC/s
Answer: 960,000 MAC operations per second. A DSP is the correct choice, because its hardware MAC unit completes each multiply-accumulate in one cycle — a general-purpose CPU would need separate multiply and add instructions plus memory fetches for the same work.
🎯 CSS Exam Angle
Examiners rarely ask "list processor types" alone. The usual framing is applied: given a scenario (embedded device, image processing, server workload), justify which processor type fits and why. Always answer with the trade-off triangle — flexibility vs speed vs power efficiency.
🔁 Repeated CSS Questions
- Classify processors and explain the suitability of each type with examples. (Frequently repeated)
- Differentiate between a microprocessor and a microcontroller. (Very frequently repeated — see MCQ trap below)
- What is a DSP? Why is it preferred over a general-purpose CPU for signal processing?
- Explain the difference between multicore processing and hyper-threading.
- Why is a GPU better suited to machine learning workloads than a CPU?
⚠️ MCQ Traps
- Microprocessor ≠ Microcontroller. A microprocessor is only the CPU and needs external RAM, ROM, and I/O chips. A microcontroller has all of these on the same chip. This is the single most repeated distinction in this topic.
- Hyper-threading does not add cores. It duplicates the register set, not the execution units.
- A GPU is SIMD, not MIMD — one instruction, many data elements.
- ASICs cannot be reprogrammed; FPGAs can. Candidates routinely swap these.