Input/Output System

CSS Optional — Paper-II, Computer Organization & Architecture

1. Definition

The I/O system is the set of hardware and control logic that interfaces the CPU and memory with external devices, handling the speed mismatch, data buffering, and error detection between fast internal components and slower peripherals.

2. Classification — I/O Techniques (high-yield comparison)

🗺️ Architecture Diagram — I/O Techniques

graph TD
    subgraph PIO["Programmed I/O"]
        CPU1["CPU polls in a loop"] --> DEV1["Device"]
    end
    subgraph INT["Interrupt-Driven I/O"]
        DEV2["Device ready"] -->|Interrupt| CPU2["CPU services ISR"]
    end
    subgraph DMAG["DMA"]
        CPU3["CPU sets up transfer"] --> DMAC["DMA Controller"]
        DMAC <-->|Direct transfer| MEM3["Memory"]
        DMAC <-->|Direct transfer| DEV3["Device"]
    end

🧮 Solved Numerical — CPU Cycles Saved by DMA (4–6-mark practice)

Question: Programmed I/O occupies 1,000 CPU cycles polling for one transfer, whereas DMA needs only 10 CPU cycles for setup and completion handling. Calculate cycles saved and percentage reduction in CPU cycles.

Given

• Programmed I/O CPU cycles = 1,000
• DMA CPU cycles = 10

Required: (i) CPU cycles saved; (ii) percentage reduction.

Formula

• Cycles saved = Programmed I/O cycles − DMA CPU cycles
• Percentage reduction = (Cycles saved / Programmed I/O cycles) × 100

Solution

1. Cycles saved = 1,000 − 10 = 990 cycles.
2. Percentage reduction = (990 / 1,000) × 100 = 99%.

Final answer: DMA saves 990 CPU cycles, corresponding to a 99% reduction in CPU cycles spent on I/O handling in this simplified example.

Explanation for marks: Programmed I/O repeatedly polls the device, while DMA transfers data between device and memory after CPU setup. DMA does not necessarily reduce total elapsed transfer time by 99%; the calculated saving concerns the stated CPU-cycle workload only.

Exam presentation (4–6 marks): Given (1), formulas (1), substitution/calculation (2), correct units and interpretation (1–2). These are suggested answer components, not an official marking scheme.

🎯 CSS Exam Angle

The compare-and-contrast question on I/O techniques is a near-guaranteed short question in every attempt. See also I/O Types for interrupt classification and BUS for the interconnection layer.

🔁 Repeated CSS Questions

1. Compare programmed I/O, interrupt-driven I/O, and DMA. (Very frequently repeated)
2. Explain the role and functions of an I/O module in a computer system.
3. Why is DMA more efficient than programmed I/O for large transfers?

⚠️ MCQ Trap

DMA still needs the CPU briefly to set up the transfer (source, destination, byte count) — it is not 100% CPU-free, just CPU-minimal.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2018 · Paper-II · Q4(C) · 6 marks

Q. In the context of I/O management, differentiate between polling and interrupts.

Ans.

2020 · Paper-II · Q2(b) · 6 marks

Q. List and briefly define two approaches to dealing with multiple interrupts.

Ans.

• 1. Sequential (disable interrupts): while one interrupt is being handled, further interrupts are disabled and stay pending. They are handled in order after the current handler finishes. It is simple but ignores priority.
• 2. Nested (priority-based): each interrupt has a priority. A higher-priority interrupt can interrupt the handler of a lower-priority one, which resumes afterwards. This gives fast response to urgent devices, but it is more complex (the handler's context must be saved).

Example: While servicing a printer interrupt, a high-priority disk controller interrupt arrives. Under sequential handling, the disk request remains pending until the printer handler returns. Under priority-nested handling, the CPU saves the printer handler's state, services the disk request, and then resumes the printer handler.

Six-mark conclusion: Sequential handling is easier to implement, while nested interrupts improve responsiveness when devices have different urgency. Masked interrupts may become pending, depending on interrupt-controller design.

2022 · Paper-II · Q4(c) · 6 marks

Q. Why is DMA access to main memory given higher priority than CPU access to main memory?

Ans.

• Time-critical devices: a device (disk, network card) transfers data at its own speed. If the DMA request is not served promptly, the device's buffer overflows and data is lost, and the device cannot be paused.
• The CPU can wait: the CPU can be delayed for a cycle without losing information, since it only runs more slowly. DMA takes memory cycles from the CPU (cycle stealing), in between the CPU's bus cycles.
• Efficiency: timely DMA service maintains device throughput and reduces the risk of buffer underrun or overrun. The CPU can often continue using registers or cache, although DMA competes for the memory bus.

Illustration: A network interface receiving packets into a small hardware buffer must promptly write the incoming data to RAM. If the CPU monopolizes memory cycles, new packets may arrive before the buffer is emptied. Giving the DMA controller timely bus access protects the incoming stream; the CPU usually tolerates a short stall.

Important qualification: Higher DMA priority is a common design choice, not an absolute rule. Modern interconnects may arbitrate bandwidth and priorities to balance latency-sensitive CPUs and I/O devices.

Conclusion (6 marks): DMA is often prioritized because I/O devices face external deadlines, whereas brief CPU stalls are usually recoverable without losing input data.

2023 · Paper-II · Q4(a) · 12 marks

Q. A 32-bit computer has two selector channels and one multiplexor channel. Each selector channel supports two magnetic disks and two magnetic tape units. The multiplexor channel has two line printers, two card readers and ten VDT terminals. Rates: disk 800 KB/s, tape 200 KB/s, line printer 6.6 KB/s, card reader 1.2 KB/s, VDT 1 KB/s. Estimate the maximum aggregate I/O transfer rate.

Model solution (12 marks)

Given: Two selector channels; each connects two disks (800 KB/s each) and two tapes (200 KB/s each). One multiplexor channel connects two printers (6.6 KB/s each), two card readers (1.2 KB/s each), and ten VDTs (1 KB/s each).

Required: Maximum aggregate transfer rate across all three channels.

Step 1 — Identify the channel rule.

• A selector channel serves one high-speed device at a time. Therefore its maximum instantaneous transfer rate is the fastest attached device's rate, not the sum of its attached device rates.
• A multiplexor channel interleaves transfers among multiple slower devices. Under the question's assumption that all devices can be serviced at their specified rates, add their rates.

Step 2 — Compute each selector channel.

Fastest attached device = magnetic disk at 800 KB/s (greater than tape at 200 KB/s).

Rate per selector channel = max(800, 800, 200, 200) = 800 KB/s.

For two independent selector channels:

2 × 800 = 1,600 KB/s.

Step 3 — Compute multiplexor channel.

• Two printers = 2 × 6.6 = 13.2 KB/s
• Two card readers = 2 × 1.2 = 2.4 KB/s
• Ten VDT terminals = 10 × 1 = 10 KB/s

Multiplexor total = 13.2 + 2.4 + 10 = 25.6 KB/s.

Step 4 — Combine all channel rates.

Maximum aggregate = 1,600 + 25.6 = 1,625.6 KB/s.

Final answer: 1,625.6 KB/s (approximately 1.626 MB/s using 1 MB = 1,000 KB).

Why this works: We add the rates across channels because the channels can operate concurrently, but we do not add the rates of devices connected to a single selector channel. The computer's 32-bit word size is not needed because the device transfer rates are already provided in KB/s.

Exam presentation — suggested 12-mark structure: Given/channel identification (2), selector-channel concept (2), selector calculation (2), multiplexor concept (2), multiplexor arithmetic (2), final aggregate with unit and interpretation (2). This is a suggested structure, not an official FPSC marking scheme.

Common traps: Multiplying 800 KB/s by the number of disks on a selector channel; omitting one of the two selector channels; adding every device on every selector channel; treating the 32-bit word size as an additional multiplier.

2023 · Paper-II · Q4(b) · 8 marks

Q. Compare unbuffered I/O with the use of a buffer. Show that the use of a buffer can reduce the running time by at most a factor of two.

Model solution (8 marks)

Concept: Without buffering, a process waits for a block transfer before continuing computation; with suitable buffering, transfer of one block can overlap with processing of another. This improves throughput.

Step 1 — Define variables.

• C = CPU computation time per block.
• T = I/O transfer time per block.
• Assume computation and transfer may overlap perfectly in steady state, with negligible buffer-management overhead.

Step 2 — Time without overlap.

For each block: C + T. Over n blocks: n(C + T).

Step 3 — Time with overlap.

In steady state, computation and I/O run concurrently; the slower activity determines throughput.

Steady-state time per block = max(C, T).

For n blocks, including pipeline fill/drain, a simple overlapping schedule takes C + T + (n − 1)max(C, T). Thus the steady-state formula is the large-n limit, not an exact equality for a single block.

Step 4 — Derive the speedup bound.

Speedup in steady state = (C + T) / max(C, T).

Case A: C ≥ T

Speedup = (C + T)/C = 1 + T/C ≤ 2.

Case B: T > C

Speedup = (C + T)/T = 1 + C/T < 2.

Therefore speedup ≤ 2, with equality in the steady-state limit when C = T.

Step 5 — Verify numerically.

Let C = 5 ms and T = 5 ms.

• Unbuffered time per block = 5 + 5 = 10 ms.
• Buffered steady-state time per block = max(5, 5) = 5 ms.
• Speedup = 10 / 5 = 2×.

Final conclusion: Under ideal overlapping conditions, buffering can at most double throughput, or reduce steady-state per-block time by 50%. For a finite number of blocks, startup/drain overhead gives a speedup below 2×.

Exam presentation — suggested 8-mark structure: definitions and assumptions (1), unbuffered timing (1), buffered timing/overlap (2), two-case proof (3), conclusion/example (1). Not an official marking scheme.

Common traps: Claiming buffering halves runtime in every situation; confusing 2× speedup with 200% time saving; forgetting that small workloads have pipeline startup/finish overhead.