P-II.I. Computer Organization & Architecture

Computer Organization & Architecture — GeeksforGeeks · tpointtech tutorial

CSS Computer Science (Optional) — Paper-II, Section-A, Topic I.

Organised by conceptual category (Foundations → Processor/CPU → Instructions & Control → Data & Arithmetic → Parallel Architecture → Memory System → I/O & Interconnection), rather than flat textbook chapter order — so topics that get compared against each other in the exam (e.g. SRAM vs DRAM, cache vs virtual memory, multiprocessor vs multicore, hardwired vs micro-programmed control) now sit together instead of being scattered across a flat list. Each subpage still follows the same internal structure: Definition → Classification → Diagram → Solved Numericals → CSS Exam Angle → Repeated Questions → MCQ Traps.

🗺️ Quick Reference — Topic → Category Map

---

📖 Topics by Category

🏛️ Foundations & Architectural Models

The conceptual groundwork — what a computer system is, how it's viewed at different abstraction levels, and the two classic organisational models everything else builds on.

🧩 Processor & CPU Design

Processor classification, internal CPU structure, how performance is measured, and the CISC/RISC design philosophies.

🔤 Instructions, Execution & Control

How an instruction is encoded, how it moves through the fetch-decode-execute cycle, and how the control unit drives that cycle.

🔢 Data Representation & Arithmetic

How numbers and characters are encoded, and how the ALU computes on them.

⚡ Parallel & Multi-Core Architecture

Extracting speed beyond a single sequential instruction stream — from pipelining inside one core up to whole systems of cores and processors.

🗂️ Memory System

The full storage stack, from the hierarchy concept down to chip-level interfacing and disk redundancy.

🔌 I/O & System Interconnection

How the CPU, memory, and peripherals are wired together and exchange data.

---

---

✅ Self-Test Questions (with Answers)

Q1. Distinguish computer architecture from computer organization.

Ans: Architecture is the programmer-visible view — what the machine does: instruction set, addressing modes, data types and formats, register set, memory model, I/O mechanisms and exception handling. It answers "what does the system do?" and changes rarely (x86 code from decades ago still runs). Organization is the hardware implementation — how it is built: control signals, buses, cache size and design, pipelining, ALU design and clocking. It answers "how is the system built?" and differs even between processors sharing one architecture (an Intel Core i3 and i9 share the x86 architecture but differ in organisation).

Q2. Explain the Fetch-Decode-Execute cycle.

Ans: (1) Fetch — the PC's address goes to the MAR, the memory word is read into the MBR/MDR and copied into the IR; the PC is incremented. (2) Decode — the control unit interprets the opcode and identifies operands and addressing modes. (3) Fetch operands — read any needed data from registers or memory (effective address calculation). (4) Execute — the ALU or control logic performs the operation. (5) Store/write back — the result goes to a register or memory. (6) Interrupt check — if an interrupt is pending, the CPU saves the PC/PSW and switches to the handler; otherwise the cycle repeats. Pipelining overlaps these stages for different instructions to raise throughput.

Q3. Compare RISC and CISC processor design philosophies.

Ans:

Modern x86 chips are hybrids: a CISC instruction set decoded internally into RISC-like micro-operations.

Q4. Why is cache memory effective, and what principle does it exploit?

Ans: It exploits the principle of locality of reference: temporal locality (a recently used item is likely to be used again soon — loop bodies, counters) and spatial locality (items near a referenced address are likely to be used soon — array traversal, sequential instructions, which is why whole blocks/lines are fetched). Because of locality, a small, fast, expensive SRAM cache can satisfy the large majority of references (hit ratios of 90–99%), so the memory system delivers nearly cache speed at nearly main-memory cost.

Q5. What is the key performance advantage of DMA over programmed I/O?

Ans: In programmed I/O the CPU executes a loop that transfers every word between the device and memory, so it is fully occupied during the transfer (and in polling it also wastes cycles checking status). With DMA, the CPU only issues one command (source, destination, count) to the DMA controller, which then transfers the entire block directly between the device and memory over the bus, interrupting the CPU only once at completion. The CPU is therefore free to execute other work during the transfer — the key advantage — giving far higher throughput for bulk transfers such as disk or network I/O. The cost is bus contention (cycle stealing) and extra hardware.

Q6. Differentiate between Von Neumann and Harvard architecture. (CSS 2017)

Ans: Von Neumann (stored-program) uses a single memory and a single bus for both instructions and data. It is simpler and cheaper and allows self-modifying code, but instruction and data fetches cannot happen at once — the Von Neumann bottleneck. Harvard uses physically separate memories and buses for instructions and data, so both can be fetched simultaneously; it allows different word sizes and access widths for each, gives better performance and some security benefit (code memory not writable), at the cost of complexity and more hardware. Von Neumann dominates general-purpose computers; Harvard suits microcontrollers and DSPs; most modern CPUs use a modified Harvard design (unified main memory, separate L1 instruction and data caches).

Q7. Explain Flynn's taxonomy with examples.

Ans: Flynn (1966) classified machines by instruction and data streams:

• SISD — single instruction, single data: a classic uniprocessor (traditional Von Neumann machine).
• SIMD — single instruction, multiple data: one instruction applied to many data items — vector processors, array processors, GPUs, x86 SSE/AVX instructions.
• MISD — multiple instructions, single data: rare and mostly theoretical; the usual example is fault-tolerant systems running the same data through different units (space shuttle flight computers).
• MIMD — multiple instructions, multiple data: independent processors on different data — multi-core CPUs, multiprocessors, clusters. MIMD is further divided into shared-memory (SMP, NUMA) and distributed-memory (clusters, MPPs).

Q8. Calculate AMAT given hit time, miss rate, and miss penalty.

Ans: AMAT = hit time + (miss rate × miss penalty). Example: hit time 1 ns, miss rate 5%, miss penalty 100 ns → AMAT = 1 + 0.05 × 100 = 6 ns. For two levels: AMAT = HT₁ + MR₁ × (HT₂ + MR₂ × MP₂). Example: L1 hit 1 ns, L1 miss 8%, L2 hit 10 ns, L2 miss 40%, memory 100 ns → AMAT = 1 + 0.08 × (10 + 0.4 × 100) = 1 + 0.08 × 50 = 5 ns. Note miss rates are local (relative to accesses reaching that level).

Q9. Represent −5 in 8-bit 2's complement.

Ans: +5 = 0000 0101. Invert all bits (1's complement) → 1111 1010. Add 1 → 1111 1011 (0xFB). Check: 1111 1011 as unsigned is 251, and 251 − 256 = −5. ✓ The 8-bit 2's-complement range is −128 to +127, and the MSB 1 marks a negative value.

Q10. Explain RAID 5 and calculate its usable capacity for a given disk configuration.

Ans: RAID 5 stripes data across all disks at block level and adds distributed parity — one parity block per stripe, rotated across the drives so no single disk becomes a bottleneck. It needs at least 3 disks, tolerates one disk failure (the lost block is rebuilt by XOR of the surviving blocks), and gives excellent read performance, but writes suffer the write penalty (read data, read parity, write data, write parity) and rebuilds are slow and risky on large drives. Usable capacity = (n − 1) × size of the smallest disk. Example: 5 disks of 2 TB → (5 − 1) × 2 = 8 TB usable (2 TB for parity, 80% efficiency). RAID 6 uses two parity blocks, giving (n − 2) × size and tolerating two failures.

Q11. Draw the memory hierarchy and explain why it works.

Ans:

^  faster, costlier per byte, smaller
|   [ CPU Registers ]        <1 ns
|   [ L1 Cache ]             ~1 ns
|   [ L2 / L3 Cache ]        ~3-20 ns
|   [ Main Memory (DRAM) ]   ~50-100 ns
|   [ SSD ]                  ~50-100 us
|   [ Hard Disk ]            ~5-10 ms
v   [ Tape / Cloud Archive ] seconds
   slower, cheaper per byte, larger

It works because of the principle of locality: programs reference a small subset of their data repeatedly (temporal) and reference neighbouring addresses (spatial). Keeping that active subset in the fast, small levels means most accesses are satisfied near the top, so the system approaches the speed of the fastest level at close to the cost per byte of the slowest. Each level acts as a cache for the level below, and data moves in blocks (cache lines, pages).

Q12. Calculate the effective access time for a three-level memory hierarchy.

Ans: Using hit rates h₁, h₂ and access times t₁, t₂, t₃ (hierarchical/successive access): EAT = h₁t₁ + (1−h₁)h₂(t₁+t₂) + (1−h₁)(1−h₂)(t₁+t₂+t₃). Example: L1 hit 90% at 2 ns, L2 hit 80% (of L1 misses) at 10 ns, memory 100 ns:

• L1 hits: 0.9 × 2 = 1.8 ns
• L1 miss, L2 hit: 0.1 × 0.8 × (2 + 10) = 0.96 ns
• Both miss: 0.1 × 0.2 × (2 + 10 + 100) = 2.24 ns
• EAT = 1.8 + 0.96 + 2.24 = 5.0 ns

State your assumption: if the levels are checked simultaneously rather than successively, drop the added upper-level times (0.9×2 + 0.08×10 + 0.02×100 = 4.6 ns).

Q13. Differentiate between cache memory and virtual memory.

Ans: Cache is a small, fast SRAM buffer between the CPU and main memory whose purpose is speed; it is managed entirely by hardware, transfers blocks/lines (32–128 bytes), and is invisible to the programmer and the OS. Virtual memory is a technique that uses disk space to extend main memory, whose purpose is capacity, isolation and protection; it is managed jointly by the OS and the MMU, transfers pages (typically 4 KB), and a miss (page fault) costs milliseconds rather than nanoseconds and causes a process switch. Both rest on the same principle of locality and use the same idea of a fast level backed by a slower one.

Archive. Old organziaont