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optional · CSS study notes

Fundamental Concepts (Architecture)

CSS Optional — Paper-II, Section-A · Chapter 7

Every question in this chapter ultimately rests on one distinction: is the question asking about what the system does (architecture) or how it is built (organization)? Get this right first.

1. Definitions

  • Computer Architecture — the attributes of a system that are visible to a programmer and have a direct impact on the logical execution of a program.
    • Includes: instruction set, data types, addressing modes, number of registers exposed to software, I/O mechanism.
    • Answers: "What does the system do?"
  • Computer Organization — the operational units and their interconnections that realize the architectural specification in actual hardware.
    • Includes: control signals, hardware technology, memory interfacing, peripheral interfaces, circuit design.
    • Answers: "How is the system built?"

2. Classification — Architecture vs Organization

AspectArchitectureOrganization
VisibilityVisible to the programmerHidden inside the hardware
Concerned withInstruction set, registers, addressing modesControl signals, buses, circuit technology
Changes acrossA family of machines (e.g., x86)Different models within the same family
Example questionIs multiplication a single instruction?Is multiplication done by a hardware multiplier or repeated addition?

Key insight worth stating in an answer: two machines can share the same architecture (the same x86 instruction set) while having completely different organizations (different pipeline depths, cache sizes, clock speeds) — this is exactly how Intel and AMD both run the same Windows binaries.

3. Architectural (Abstraction) Levels

Computer systems are understood as a stack of abstraction levels, each hiding the complexity of the one below it:

  1. Digital logic level — gates, flip-flops, physical circuits.
  2. Microarchitecture level — datapath, control unit, register transfers.
  3. Instruction Set Architecture (ISA) level — the machine-language interface: opcodes, registers, addressing modes.
  4. Operating system level — extends the ISA with system calls, virtual memory, file abstractions.
  5. Assembly language level — human-readable mnemonics mapped to machine code.
  6. High-level language level — C, Java, Python — compiled or interpreted down through every level above.

🗺️ Architecture Diagram — Levels of Abstraction

graph TD
    L6["High-Level Language
C, Java, Python"] --> L5["Assembly Language"]
    L5 --> L4["Operating System"]
    L4 --> L3["Instruction Set Architecture (ISA)"]
    L3 --> L2["Microarchitecture
datapath, control unit"]
    L2 --> L1["Digital Logic
gates, flip-flops"]

4. Virtual Machines (brief)

  • Definition — a software abstraction that emulates a complete computer system, letting software built for one platform run isolated on different underlying hardware.
  • Full classification (process vs system VM, Type 1 vs Type 2 hypervisor) is covered on the dedicated Virtual Machines page.

🎯 CSS Exam Angle

The Architecture vs Organization distinction is the single most repeated definitional question in this chapter — almost every attempt asks it in some form. Always answer with the comparison table above, plus one concrete example (same ISA, different organization).

🔁 Repeated CSS Questions

  1. Differentiate between computer architecture and computer organization with examples. (Very frequently repeated)
  2. Explain the different architectural levels from digital logic to high-level language.
  3. What is a virtual machine, and how does it relate to architectural abstraction?

⚠️ MCQ Trap

Architecture = programmer-visible attributes (instruction set, registers); Organization = how it is actually implemented in hardware. Two machines with identical architecture can have entirely different organizations.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2025 · Paper-II · Q2(a) · 3 marks

Q. An instruction needs five stages: fetch 30 ns, decode 9 ns, execute 20 ns, memory access 35 ns, store results 10 ns. The instruction must pass through the stages in sequence. What is the minimum asynchronous time for any single instruction to complete?

Ans.

  • The stages cannot overlap for a single instruction, so the times add up: 30 + 9 + 20 + 35 + 10 = 104 ns.
  • (With a synchronous pipeline the clock would have to match the slowest stage, 35 ns, so one instruction would take 5 × 35 = 175 ns. The asynchronous minimum is the plain sum.)

MCQs

2025 P-II · Q1. A stack is:

  • (A) An 8-bit register in a microprocessor
  • (B) A 16-bit register in a microprocessor
  • (C) A set of memory locations in R/W memory reserved for storing information temporarily during the execution of a program ✅
  • (D) A 16-bit memory address stored in the program counter
  • Answer: (C).
  • Why: the stack is an area of read/write memory used for return addresses, parameters and temporary data (last in, first out). It is tracked by a stack pointer register, but the stack itself is not a register.

2025 P-II · Q2. Data hazards occur when:

  • (A) There is greater performance loss
  • (B) The pipeline changes the order of read/write access to operands ✅
  • (C) Some functional unit is not fully pipelined
  • (D) The machine size is limited
  • Answer: (B).
  • Why: a data hazard appears when instructions overlap in the pipeline and one needs an operand before an earlier instruction has written it, so the order of reads and writes differs from sequential order (RAW, WAR, WAW). Option (C) describes a structural hazard.

2026 P-II · Q4. In a pipelined processor, what is the primary purpose of the instruction pipeline?

  • (A) To increase the clock speed of the processor
  • (B) To execute multiple instructions simultaneously ✅
  • (C) To reduce the number of instructions in a program
  • (D) None of these
  • Answer: (B).
  • Why: a pipeline overlaps the stages (fetch, decode, execute, write-back) of several instructions, so more instructions are completed per unit time. It does not raise the clock speed by itself or change the program.

2026 P-II · Q18. You get a hardware resource conflict. It will more likely be an IRQ conflict rather than an I/O conflict because:

  • (A) The BIOS sometimes has more of a problem controlling IRQs
  • (B) I/O addresses cannot conflict
  • (C) There are a lot more I/O addresses than IRQs ✅
  • (D) None of these
  • Answer: (C).
  • Why: a PC has only 16 IRQ lines but thousands of I/O port addresses, so devices run out of IRQs and share them far sooner. Option (B) is false, since I/O addresses can also conflict.

2024 P-II · Q10. In the RISC architecture, the _ is updated whenever a function is called:

  • (A) Frame pointer and Return address register
  • (B) Stack pointer
  • (C) Both (A) and (B) ✅
  • (D) None of these
  • Answer: (C) Both (A) and (B) (best reading).
  • Why: a call instruction sets the return-address register (for example ra in MIPS), and the function's prologue moves the stack pointer and frame pointer to build the new stack frame, so all of them change.
  • Note: the question is ambiguous. The official key may be (A) if only the hardware side of the call is meant.