BUS

CSS Optional — Paper-II, Section-A · Chapter 7 · 🔥 High-yield numerical topic

The bus is the shared set of electrical pathways that lets the CPU, memory, and I/O devices exchange information. It is what makes a computer modular — any device that follows the bus protocol can be attached without redesigning the CPU.

🗺️ Architecture Diagram — System Bus Structure

graph LR
    CPU["CPU"] <--> ABUS["Address Bus
unidirectional, CPU to Memory/IO"]
    CPU <--> DBUS["Data Bus
bidirectional"]
    CPU <--> CBUS["Control Bus
R/W, Clock, Interrupts"]
    ABUS --> MEM["Main Memory"]
    DBUS <--> MEM
    CBUS --> MEM
    ABUS --> IO["I/O Devices"]
    DBUS <--> IO
    CBUS --> IO

1. The Three System Buses

Typical control signals: Memory Read, Memory Write, I/O Read, I/O Write, Bus Request, Bus Grant, Interrupt Request, Interrupt Acknowledge, Clock, Reset.

The distinction that carries the marks: address bus width sets the size of the memory space; data bus width sets the speed of transfer. A machine may have a 32-bit address bus (4 GB addressable) with only a 16-bit data bus (2 bytes per transfer). These are independent design choices.

2. Bus Structures

• Single-bus (unified) — one bus shared by everything. Cheap and simple, but only one transfer can occur at a time, so contention is severe.
• Multiple-bus hierarchy — a fast local bus close to the CPU, a system bus for memory, and slower expansion buses for peripherals. Isolates slow devices so they do not throttle CPU-memory traffic. This is how real systems are built.
• Synchronous bus — all transfers are timed to a common clock. Simple and fast, but every device must keep up with the clock, so the slowest device constrains the design.
• Asynchronous bus — transfers use handshaking signals rather than a shared clock. Accommodates devices of very different speeds, at the cost of protocol overhead.

3. Bus Arbitration

When multiple devices want the bus simultaneously, an arbitration mechanism decides who gets it.

Centralised arbitration — a single bus arbiter grants access:

• Daisy chaining — the grant signal passes physically down a chain of devices; the first requesting device takes it. Very few wires needed, but priority is fixed by physical position, and a failed device breaks the chain for everyone downstream.
• Polling — the arbiter queries each device in turn. Priority is programmable, but polling takes time.
• Independent request lines — every device has its own request and grant line. Fastest and most flexible, but requires the most wiring.

Distributed arbitration — devices negotiate among themselves without a central arbiter, typically by comparing priority codes placed on shared lines. More robust (no single point of failure) but more complex per device.

4. Key Formulas

$$\text{Addressable locations} = 2^{n} \quad (n = \text{address bus width in bits})$$ $$\text{Total memory capacity} = 2^{n} \times \text{word size (bytes)}$$ $$\text{Bus bandwidth (bytes/s)} = \frac{\text{Bus width (bits)}}{8} \times \text{Bus clock frequency}$$ $$\text{Transfer time} = \frac{\text{Data size}}{\text{Bandwidth}}$$

For a DDR (double data rate) bus, which transfers on both the rising and falling clock edges:

$$\text{Bandwidth} = \frac{\text{Bus width}}{8} \times \text{Clock frequency} \times 2$$

---

🧮 Solved Numerical 1 — Addressable Memory

Q: A system has a 32-bit address bus and is byte-addressable. What is the maximum memory it can address?

Given: $n = 32$ (byte-addressable)

Solution:

$$\begin{aligned} \text{Locations} &= 2^{n} = 2^{32} = 4{,}294{,}967{,}296 \text{ bytes} \\ \text{In GB} &= \frac{4{,}294{,}967{,}296}{1024^{3}} = \frac{4{,}294{,}967{,}296}{1{,}073{,}741{,}824} = 4\ \text{GB} \end{aligned}$$

Answer: 4 GB.

This is the architectural reason 32-bit operating systems could never use more than 4 GB of RAM.

🧮 Solved Numerical 2 — Word-Addressable Memory

Q: A system has a 20-bit address bus and each addressable location stores one 16-bit word. Find the total memory capacity in bytes.

Given: $n = 20$, word size = 16 bits = 2 bytes

Solution:

$$\begin{aligned} \text{Locations} &= 2^{20} = 1{,}048{,}576 \\ \text{Capacity} &= 1{,}048{,}576 \times 2 = 2{,}097{,}152 \text{ bytes} = 2\ \text{MB} \end{aligned}$$

Answer: 2 MB.

⚠️ Notice the difference from Numerical 1: with byte-addressable memory, 2ⁿ gives bytes directly. With word-addressable memory you must multiply by the word size. Read the question wording carefully — this is a deliberate exam trap.

🧮 Solved Numerical 3 — Bus Bandwidth

Q: A bus is 64 bits wide and operates at 100 MHz. Calculate its bandwidth.

Given: bus width = 64 bits, clock = 100 MHz

Solution:

$$\begin{aligned} \text{Bandwidth} &= \frac{64}{8} \times 100 \times 10^{6} \\ &= 8 \times 100{,}000{,}000 \\ &= 800{,}000{,}000\ \text{bytes/s} = 800\ \text{MB/s} \end{aligned}$$

Answer: 800 MB/s.

🧮 Solved Numerical 4 — DDR Bus Bandwidth

Q: A DDR memory bus is 64 bits wide at 200 MHz, transferring on both clock edges. Find its bandwidth.

Given: bus width = 64 bits, clock = 200 MHz, DDR (2 transfers per cycle)

Solution:

$$\begin{aligned} \text{Bandwidth} &= \frac{64}{8} \times 200 \times 10^{6} \times 2 \\ &= 8 \times 200{,}000{,}000 \times 2 \\ &= 3{,}200{,}000{,}000\ \text{bytes/s} = 3.2\ \text{GB/s} \end{aligned}$$

Answer: 3.2 GB/s. The ×2 factor is exactly what "double data rate" means — the clock is unchanged, but two transfers occur per cycle.

🧮 Solved Numerical 5 — Transfer Time

Q: How long does it take to transfer a 4 MB file over an 800 MB/s bus?

Given: data size = 4 MB, bandwidth = 800 MB/s

Solution:

$$\begin{aligned} \text{Transfer time} &= \frac{\text{Data size}}{\text{Bandwidth}} \\ &= \frac{4}{800} = 0.005\ \text{s} = 5\ \text{ms} \end{aligned}$$

Answer: 5 ms.

🧮 Solved Numerical 6 — Determining Required Bus Width

Q: A system must address 1 GB of byte-addressable memory. What is the minimum address bus width required?

Solution:

$$\begin{aligned} 1\ \text{GB} &= 2^{30}\ \text{bytes} \\ 2^{n} &\geq 2^{30} \;\Rightarrow\; n = 30\ \text{bits} \end{aligned}$$

Answer: 30 address lines minimum.

🧮 Solved Numerical 7 — Combined Bus Design Problem

Q: A memory system has 16 MB of byte-addressable memory and a data bus that transfers 4 bytes per access at 50 MHz. Determine (a) the address bus width and (b) the peak bandwidth.

(a) Address bus width:

$$16\ \text{MB} = 16 \times 2^{20} = 2^{4} \times 2^{20} = 2^{24}\ \text{bytes} \;\Rightarrow\; n = 24\ \text{address lines}$$

(b) Bandwidth:

$$\begin{aligned} \text{Bandwidth} &= 4 \times 50 \times 10^{6} \\ &= 200{,}000{,}000\ \text{bytes/s} = 200\ \text{MB/s} \end{aligned}$$

Answer: 24-bit address bus; 200 MB/s peak bandwidth.

---

🎯 CSS Exam Angle

The 2ⁿ addressable-memory calculation is among the most reliably repeated numericals in the entire paper, often appearing as a one-mark MCQ or a short calculation. Bandwidth questions are close behind.

For full marks:

1. State whether the memory is byte- or word-addressable before calculating — this determines whether you multiply by word size.
2. Show the power-of-two conversion explicitly (2³² = 4,294,967,296 = 4 GB), rather than jumping to the answer.
3. Always attach units — MB/s, GB, ms.

🔁 Repeated CSS Questions

1. Given an n-bit address bus, calculate the maximum addressable memory. (Numerical — very frequently repeated)
2. Differentiate between the address bus, data bus, and control bus. (Frequently repeated)
3. Explain bus arbitration techniques — daisy chaining, polling, and independent request lines.
4. Calculate the bandwidth of a bus given its width and clock frequency. (Numerical)
5. Differentiate between synchronous and asynchronous bus operation.
6. What is bus contention, and how does a multiple-bus hierarchy reduce it?

⚠️ MCQ Traps

• Address bus width determines memory size; data bus width determines transfer speed. These are swapped in MCQs more often than any other pair in this topic.
• The address bus is unidirectional (CPU outward); the data bus is bidirectional. Candidates frequently mark the address bus as bidirectional.
• Byte-addressable vs word-addressable changes the answer. 2ⁿ gives locations, not automatically bytes.
• DDR doubles bandwidth without doubling the clock — the frequency is unchanged; transfers per cycle double.
• Daisy chaining gives fixed priority by physical position and fails for all downstream devices if one link breaks — its defining weakness.
• Increasing the data bus width does not let the system address more memory, and increasing the address bus width does not make transfers faster.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2018 · Paper-II · Q2(B) · 6 marks

Q. Differentiate between the address bus, data bus and control bus.

Ans.

2019 · Paper-II · Q2(c) · 6 marks

Q. List all basic functions of buses in the context of computer architecture.

Ans.

• Data transfer: move data and instructions between CPU, memory and I/O devices.
• Addressing: select the source or destination location (address bus).
• Control and timing: carry read/write commands, clock and interrupt signals.
• Synchronisation between components working at different speeds.
• Arbitration: decide which device (CPU, DMA controller) may use the shared bus.
• Interconnection: connect all system components and allow expansion (adding devices).
• Bus performance: transfer capacity depends on bus width, transfer frequency and protocol overhead. Theoretical peak data rate = (data-bus width in bits ÷ 8) × transfers per second, excluding overhead. Power delivery is a feature of certain external interfaces, not a basic function of the CPU–memory system bus.

6-mark exam presentation: Define a bus (1 mark); explain data, address and control functions (3 marks); explain synchronization and arbitration with a CPU–DMA example (2 marks). This is suggested practice allocation, not an official marking scheme.