Machine Instructions

CSS Optional — Paper-II, Section-A · Chapter 7 · 🔥 Frequently repeated topic

An instruction is the fundamental unit of work a CPU understands. This topic covers how instructions are encoded (instruction format), what kinds exist (instruction types), and how they locate their operands (addressing modes — the highest-yield part).

🗺️ Architecture Diagram — Instruction Format and Addressing Modes

graph TD
    INSTR["Instruction"] --> OP["Opcode Field
what to do"]
    INSTR --> ADDR["Operand / Address Field
where the data is"]
    ADDR --> IMM["Immediate: value in instruction"]
    ADDR --> DIR["Direct: EA = address field"]
    ADDR --> IND["Indirect: EA = Mem of address field"]
    ADDR --> REGM["Register: operand in Rn"]
    ADDR --> REGI["Register Indirect: EA = Rn"]
    ADDR --> IDX["Indexed: EA = Base + Index"]
    ADDR --> REL["Relative: EA = PC + Offset"]

1. Instruction Format

Every machine instruction has two parts:

┌──────────┬─────────────────────────────┐
│  OPCODE  │   OPERAND / ADDRESS FIELD   │
└──────────┴─────────────────────────────┘

• Opcode — specifies what operation to perform. If a machine supports 2ᵏ operations, the opcode needs k bits.
• Operand field(s) — specify where the data is. May contain a register number, a memory address, or an immediate value.

Format length trade-off: fixed-length instructions (RISC) simplify decoding and enable pipelining; variable-length instructions (CISC) save memory but complicate decoding. See CISC vs RISC.

2. Instruction Types

Note: data transfer instructions never change the data; they only relocate it. Control transfer instructions work by overwriting the PC.

3. Addressing Modes ⭐ (highest-yield section)

An addressing mode is the rule by which the CPU computes the effective address (EA) — the actual location of the operand.

Why so many modes? The address field of an instruction is small, but programs need constants, variables, pointers, arrays, records and branches. Each mode is a different rule for turning the few bits in the instruction into the real location of the data, so a short instruction can still reach any data in memory.

Notation used below:

• $A$ — the address (or value) field of the instruction
• $R$ and $(R)$ — a register, and the contents of that register
• $M[x]$ — the contents of memory location $x$
• $EA$ — the effective address, the final address of the operand
• $PC$ — program counter, $XR$ — index register, $BR$ — base register
• Mode field: a few bits of the instruction (the mode bits) tell the CPU which rule to apply.

How to Read the Assembly Examples

The examples below use a simple textbook accumulator machine, so that one line of assembly shows one idea. It is not a real assembler, but real ones (MIPS, x86) follow the same pattern, and they are explained at the end of this subsection.

• Instruction form: OPCODE operand ; comment. The text after ; is only a comment for the reader.
• The accumulator ACC is implied. In ADD 500 the first operand and the destination is always ACC, so it means $ACC \leftarrow ACC + \text{(the operand found by the mode)}$.
• The way the operand is written decides the mode:

• The arrow $\leftarrow$ means "is replaced by" (a register transfer): $ACC \leftarrow M[500]$ copies the contents of location 500 into ACC.

What the CPU does for one instruction (taking ADD 500 as the example). Every instruction goes through the instruction cycle:

$$\begin{aligned} \text{Fetch:}\quad & MAR \leftarrow PC, \quad MBR \leftarrow M[MAR], \quad IR \leftarrow MBR, \quad PC \leftarrow PC + 1 \\ \text{Decode:}\quad & \text{opcode} = ADD, \quad \text{mode} = \text{direct}, \quad A = 500 \\ \text{Operand fetch:}\quad & MAR \leftarrow 500, \quad MBR \leftarrow M[MAR] \\ \text{Execute:}\quad & ACC \leftarrow ACC + MBR \end{aligned}$$

Only the operand-fetch step changes from one mode to the next. This is what each assembly form makes the hardware do:

A small program, line by line (direct and immediate modes together). The task is to add 5 to the number stored at location 500 and keep the result at location 504:

LOAD  500     ; ACC <- M[500]     (direct)
ADD   #5      ; ACC <- ACC + 5    (immediate)
STORE 504     ; M[504] <- ACC     (direct)

Trace when $M[500] = 30$:

$$\begin{aligned} \text{LOAD 500:}\quad & ACC = M[500] = 30 \\ \text{ADD \#5:}\quad & ACC = 30 + 5 = 35 \\ \text{STORE 504:}\quad & M[504] = ACC = 35 \end{aligned}$$

Why indexed addressing suits arrays: the instruction ADD 3000(XR) is written once, and only the register changes in each loop pass. With the array at 3000 and 4-byte elements:

$$\begin{aligned} XR = 0:\quad & EA = 3000 + 0 = 3000 \quad (A[0]) \\ XR = 4:\quad & EA = 3000 + 4 = 3004 \quad (A[1]) \\ XR = 8:\quad & EA = 3000 + 8 = 3008 \quad (A[2]) \end{aligned}$$

Real assembly languages use the same ideas with a different syntax:

• MIPS lw $t0, 8($s1): lw is load word, $t0 is the destination register, and 8($s1) is the displacement 8 plus the base register $s1. As a transfer: $t0 \leftarrow M[(s1) + 8]$.
• x86 MOV EAX, [EBX + ESI*4 + 8]: MOV copies into the first operand (the destination comes first), EAX is the destination, and the square brackets mean "the memory at the address inside". The address is base EBX + index ESI × scale 4 + displacement 8. As a transfer: $EAX \leftarrow M[EBX + 4 \times ESI + 8]$.
• Implied mode: CLC (clear carry flag) and INC have no operand field, because the opcode already says what to act on.

(a) Immediate Addressing

The operand is the value, stored inside the instruction itself.

Assembly: ADD #5 (add the literal value 5)

$$\text{Operand} = A = 5 \qquad \text{(no effective address, no memory access)}$$

Example: with $ACC = 20$:

$$ACC \leftarrow ACC + 5 = 20 + 5 = 25$$

• ✅ Fastest — zero memory references beyond the instruction fetch.
• ❌ Operand size limited by the field width; the value is fixed at compile time.
• Use: initialising constants, loop counters.

(b) Direct (Absolute) Addressing

The instruction contains the address of the operand.

Assembly: ADD 500 (add the contents of memory location 500)

$$EA = A = 500 \qquad \text{Operand} = M[500]$$

Example: with $M[500] = 30$ and $ACC = 20$:

$$ACC \leftarrow ACC + M[500] = 20 + 30 = 50$$

• ✅ Simple; one memory access for the operand.
• ❌ Address space limited by field width; address fixed at compile time.

(c) Indirect Addressing

The instruction contains the address of a location that itself contains the operand's address — a double dereference.

Assembly: ADD (500) (location 500 holds the real address)

$$EA = M[A] = M[500] \qquad \text{Operand} = M[EA]$$

Example: with $M[500] = 800$, $M[800] = 30$ and $ACC = 20$:

$$\begin{aligned} EA &= M[500] = 800 \\ \text{Operand} &= M[800] = 30 \\ ACC &\leftarrow 20 + 30 = 50 \end{aligned}$$

• ✅ Large address space reachable from a small field; supports pointers.
• ❌ Two memory accesses to fetch one operand — slow.

(d) Register Addressing

The operand is in a CPU register.

Assembly: ADD R1 (the operand is the contents of R1)

$$\text{Operand} = (R1) \qquad \text{(no memory access)}$$

Example: with $R1 = 25$ and $ACC = 20$:

$$ACC \leftarrow 20 + 25 = 45$$

• ✅ Fastest operand access after immediate — no memory reference at all; short instruction encoding.
• ❌ Limited by the number of registers available.

(e) Register Indirect Addressing

The register holds the address of the operand.

Assembly: ADD (R1)

$$EA = (R1) \qquad \text{Operand} = M[(R1)]$$

Example: with $R1 = 200$, $M[200] = 35$ and $ACC = 20$:

$$EA = 200 \;\Rightarrow\; ACC \leftarrow 20 + M[200] = 20 + 35 = 55$$

• ✅ One memory access; the address can be computed at runtime — the basis of pointer arithmetic in C.

(f) Indexed Addressing

$$EA = A + (XR) \qquad \text{Operand} = M[EA]$$

Here $A$ is the start of the array (in the instruction) and $(XR)$ is the contents of the index register (element number × element size).

Example: the array starts at 3000 and $XR = 12$ (element 3 × 4 bytes):

$$EA = 3000 + 12 = 3012$$

• The workhorse of array access. The base is the array's start; the index register holds the element number (scaled by element size).
• ✅ Enables loops over arrays with a single instruction per iteration.

(g) Base-Register (Displacement) Addressing

$$EA = (BR) + D \qquad \text{Operand} = M[EA]$$

Here $(BR)$ is the contents of the base register and $D$ is the displacement (offset) in the instruction.

Example: a record is loaded at 6000 ($BR = 6000$) and the field is at offset 24:

$$EA = 6000 + 24 = 6024$$

If the operating system moves the record, only $BR$ changes, and the instruction stays the same. That is why this mode helps relocation.

• Similar arithmetic to indexed, but the base is in a register and the offset is constant, whereas indexed has a constant base and a varying register index. Used for accessing fields within a structure and for relocatable code.

(h) Relative (PC-Relative) Addressing

$$EA = (PC) + \text{Offset}$$

Example: $PC = 1000$ (already pointing to the next instruction) and the offset is $+40$:

$$EA = 1000 + 40 = 1040 \qquad \text{(the branch target)}$$

• Used for branches. Because the target is expressed as a distance rather than an absolute address, the code can be loaded anywhere in memory without modification — this is what makes position-independent code possible.

(i) Implied / Implicit Addressing

The operand is implicit in the opcode itself.

CLC           ; clear carry flag — no operand field at all
INC           ; increment the accumulator

(j) Auto-increment and Auto-decrement

Register indirect addressing in which the register is updated automatically by the size of the operand $d$ (1, 2 or 4 bytes).

$$\begin{aligned} \text{Auto-increment:}\quad & EA = (R), \quad \text{then } R \leftarrow R + d \\ \text{Auto-decrement:}\quad & R \leftarrow R - d, \quad \text{then } EA = (R) \end{aligned}$$

Example: $R = 1000$ and $d = 4$:

$$\begin{aligned} \text{Auto-increment, 1st access:}\quad & EA = 1000, \quad R = 1004 \\ \text{Auto-increment, 2nd access:}\quad & EA = 1004, \quad R = 1008 \\ \text{Auto-decrement:}\quad & R = 1000 - 4 = 996, \quad EA = 996 \end{aligned}$$

• ✅ Steps through an array or string with no separate increment instruction. Together they also give the stack operations PUSH (decrement, then store) and POP (load, then increment).
• ❌ The register changes as a side effect, which complicates pipelining and exception handling.

(k) Scaled Index Addressing (x86)

The element number is multiplied by the element size inside the address calculation.

$$EA = (\text{Base}) + (\text{Index}) \times \text{Scale} + \text{Displacement}$$

Example: MOV EAX, [EBX + ESI*4 + 8] with $EBX = 1000$, $ESI = 5$:

$$EA = 1000 + 5 \times 4 + 8 = 1028$$

• ✅ One instruction reaches element $i$ of an array of 4-byte items, so the programmer does not scale the index by hand.
• ❌ Complex address hardware, so it is found in CISC but not in RISC.

(l) Stack Addressing

The operand is at the top of the stack, and the stack pointer (SP) gives its address, so the instruction needs no address field (zero-address instructions such as ADD, PUSH, POP).

$$\begin{aligned} \text{PUSH:}\quad & SP \leftarrow SP - d, \quad M[SP] \leftarrow \text{operand} \\ \text{POP:}\quad & \text{operand} \leftarrow M[SP], \quad SP \leftarrow SP + d \end{aligned}$$

Example: $SP = 5000$, $d = 4$ (the stack grows downward):

$$\text{PUSH:}\quad SP = 5000 - 4 = 4996, \qquad \text{POP:}\quad SP = 4996 + 4 = 5000$$

• Use: evaluating expressions and handling procedure calls (return address, parameters, local variables).

Which Mode for Which Job

Summary Table

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🧮 Solved Numerical 1 — Effective Address Across Modes

Q: Given: instruction address field = 400, Memory[400] = 700, Memory[700] = 900, R1 = 200, Memory[200] = 350, PC = 1000, Index register = 50, Memory[450] = 520, Memory[1400] = 640. Find the operand under each addressing mode.

Given: $A = 400$, $M[400] = 700$, $M[700] = 900$, $R1 = 200$, $M[200] = 350$, $PC = 1000$, $XR = 50$, $M[450] = 520$, $M[1400] = 640$.

Step-by-step working:

$$\begin{aligned} \text{Immediate:}\quad & \text{Operand} = A = 400 \\ \text{Direct:}\quad & EA = A = 400 \;\Rightarrow\; \text{Operand} = M[400] = 700 \\ \text{Indirect:}\quad & EA = M[400] = 700 \;\Rightarrow\; \text{Operand} = M[700] = 900 \\ \text{Register:}\quad & \text{Operand} = (R1) = 200 \\ \text{Register indirect:}\quad & EA = (R1) = 200 \;\Rightarrow\; \text{Operand} = M[200] = 350 \\ \text{Indexed:}\quad & EA = A + XR = 400 + 50 = 450 \;\Rightarrow\; \text{Operand} = M[450] = 520 \\ \text{Relative:}\quad & EA = PC + A = 1000 + 400 = 1400 \;\Rightarrow\; \text{Operand} = M[1400] = 640 \end{aligned}$$

Result table:

Answer as above. This single-table format — one set of given values, every mode applied — is precisely how this question is usually set, so practise it in exactly this layout.

🧮 Solved Numerical 2 — Array Access via Indexed Addressing

Q: An integer array starts at address 3000. Each element is 4 bytes. Using indexed addressing, find the effective address of element A[7].

Given: base address $B = 3000$, element size $s = 4$ bytes, index $i = 7$ (indexing starts at 0).

Formula:

$$EA = B + i \times s$$

Working:

$$\begin{aligned} EA &= 3000 + (7 \times 4) \\ &= 3000 + 28 \\ &= 3028 \end{aligned}$$

If the array is numbered from 1 (Pascal, FORTRAN), the formula becomes:

$$EA = B + (i - 1) \times s = 3000 + (7 - 1) \times 4 = 3024$$

Answer: 3028.

Note the scaling by element size — omitting it is a common error. Element A[0] is at 3000, A[1] at 3004, and so on.

🧮 Solved Numerical 3 — Instruction Format Design

Q: A machine has a 16-bit instruction, must support 32 distinct operations, and uses direct addressing. How many memory locations can it address?

Given: instruction length = 16 bits, number of operations = 32, direct addressing.

Step 1 — Opcode bits:

$$\text{Opcode bits} = \lceil \log_{2} 32 \rceil = 5$$

Step 2 — Address bits:

$$\text{Address bits} = 16 - 5 = 11$$

Step 3 — Addressable locations:

$$\text{Locations} = 2^{11} = 2{,}048$$

Answer: 2,048 locations.

Follow-up worth adding in the exam: this illustrates the fundamental tension in instruction format design — every bit given to the opcode is a bit taken from the address field. Supporting more operations means addressing less memory. Indirect addressing exists precisely to escape this limit.

🧮 Solved Numerical 4 — Memory Accesses and Timing

Q: Each memory access takes 20 ns. Compare the total operand-fetch time for direct versus indirect addressing.

Given: memory access time $t_{mem} = 20\ \text{ns}$.

Formula:

$$T_{operand} = (\text{number of memory accesses}) \times t_{mem}$$

Working:

$$\begin{aligned} \text{Immediate or register:}\quad & 0 \times 20 = 0\ \text{ns} \\ \text{Direct:}\quad & 1 \times 20 = 20\ \text{ns} \\ \text{Indirect:}\quad & 2 \times 20 = 40\ \text{ns} \\ \text{Ratio:}\quad & \frac{T_{indirect}}{T_{direct}} = \frac{40}{20} = 2 \end{aligned}$$

Answer: Direct 20 ns, Indirect 40 ns — indirect is 2× slower. This is the concrete cost of the flexibility indirect addressing provides.

🧮 Solved Numerical 5 — Relative Branch Range

Q: A branch instruction uses PC-relative addressing with a signed 8-bit offset. If PC = 5000, what is the range of addresses the branch can reach?

Given: $PC = 5000$, offset is a signed 8-bit number.

Step 1 — Offset range:

$$-2^{7} \le \text{Offset} \le 2^{7} - 1 \quad\Rightarrow\quad -128 \le \text{Offset} \le +127$$

Step 2 — Target range:

$$\begin{aligned} EA_{min} &= PC - 128 = 5000 - 128 = 4872 \\ EA_{max} &= PC + 127 = 5000 + 127 = 5127 \end{aligned}$$

Step 3 — Number of reachable addresses:

$$2^{8} = 256$$

Answer: 4872 to 5127. This limited range is why compilers occasionally generate a "branch to a jump" — the intended target lies outside the reachable window.

🧮 Solved Numerical 6 — Instruction Format with a Mode Field

Q: A 16-bit instruction has a 4-bit opcode and a 3-bit addressing-mode field. The remaining bits form the address field. How many operations and modes can it support, and how much memory can the address field reach directly?

Step-by-step working:

$$\begin{aligned} \text{Operations} &= 2^{4} = 16 \\ \text{Addressing modes} &= 2^{3} = 8 \\ \text{Address bits} &= 16 - 4 - 3 = 9 \\ \text{Addressable locations} &= 2^{9} = 512 \end{aligned}$$

Answer: 16 operations, 8 modes, 512 locations. Every extra field takes bits from the address field. Without the mode field the same instruction could address $2^{12} = 4{,}096$ locations, and the modes are what let it reach the rest of memory indirectly.

🧮 Solved Numerical 7 — Average Memory Accesses per Instruction

Q: Each instruction has one instruction fetch and one operand. The operand modes are immediate 10%, register 40%, direct 20%, indirect 10% and indexed 20%. A memory access takes 20 ns. Find the average memory accesses per instruction and the average memory time.

Step 1 — Check the fractions:

$$0.10 + 0.40 + 0.20 + 0.10 + 0.20 = 1.00$$

Step 2 — Operand accesses for each mode: immediate 0, register 0, direct 1, indirect 2, indexed 1.

Step 3 — Average operand accesses:

$$\begin{aligned} \bar{a} &= \sum F_i \times a_i \\ &= (0.10 \times 0) + (0.40 \times 0) + (0.20 \times 1) + (0.10 \times 2) + (0.20 \times 1) \\ &= 0 + 0 + 0.20 + 0.20 + 0.20 = 0.60 \end{aligned}$$

Step 4 — Add the instruction fetch and find the time:

$$\begin{aligned} \text{Accesses per instruction} &= 1 + 0.60 = 1.60 \\ T_{mem} &= 1.60 \times 20\ \text{ns} = 32\ \text{ns} \end{aligned}$$

Answer: 1.60 accesses and 32 ns per instruction. Indirect addressing is only 10% of the operands but causes $\frac{0.20}{0.60} \approx 33\%$ of the operand accesses, which is the cost of its flexibility. The instruction fetch is counted in the total, as in the effective-CPI problems on the Performance Metrics page.

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🎯 CSS Exam Angle

Addressing modes are among the most repeated short questions in this chapter. Examiners almost always want:

1. The mode named, defined, and given an example — not just listed.
2. The effective address formula written explicitly for each.
3. A worked example showing the operand actually retrieved (Numerical 1's layout).
4. A closing line on the trade-off: speed decreases as flexibility increases, from immediate (0 memory accesses) through to indirect (2).

Mentioning why each mode exists — indexed for arrays, relative for relocatable code, register indirect for pointers — is what lifts an answer above a memorised list.

🔁 Repeated CSS Questions

1. Explain the different addressing modes with examples. (Very frequently repeated — treat as near-certain)
2. Differentiate between direct and indirect addressing modes. (MCQ favourite)
3. What is an instruction format? Explain the roles of the opcode and operand fields.
4. Calculate the effective address for a given addressing mode and set of values. (Numerical)
5. Which addressing mode is most suitable for accessing array elements, and why?
6. Given an instruction length and number of operations, determine the addressable memory. (Numerical)
7. Classify machine instructions by type with examples.

⚠️ MCQ Traps

• Indirect addressing requires TWO memory accesses, direct requires one, and immediate/register require zero. Access count is the most common MCQ discriminator here.
• In indirect addressing the field holds the address OF an address, not the data. Candidates routinely describe direct addressing when asked about indirect.
• Immediate addressing is the fastest, but the operand is fixed at compile time and cannot be a variable.
• Indexed vs base-register addressing: in indexed mode the base is constant and the index register varies; in base-displacement mode the base register varies and the offset is constant. The arithmetic is identical; the roles are reversed.
• Relative addressing is used for branches, not for data access, and it is what makes position-independent code possible.
• A larger opcode field means a smaller address field in a fixed-length instruction — they compete for the same bits.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2021 · Paper-II · Q2(a) · 10 marks

Q. Examine any five addressing modes with an example based on the contents of the address field, the actual (effective) address and the contents of the memory location.

Ans. Assume the address field A = 500, register R1 = 400, and memory: M[500] = 800, M[800] = 300, M[400] = 250, M[900] = 700.

Working in equation form (with the assumed values A = 500, R1 = 400, M[500] = 800, M[800] = 300, M[400] = 250, M[900] = 700):

$$\begin{aligned} \text{Immediate:}\quad & \text{Operand} = A = 500 \\ \text{Direct:}\quad & EA = A = 500 \;\Rightarrow\; \text{Operand} = M[500] = 800 \\ \text{Indirect:}\quad & EA = M[500] = 800 \;\Rightarrow\; \text{Operand} = M[800] = 300 \\ \text{Register direct:}\quad & \text{Operand} = (R1) = 400 \\ \text{Register indirect:}\quad & EA = (R1) = 400 \;\Rightarrow\; \text{Operand} = M[400] = 250 \\ \text{Displacement:}\quad & EA = A + (R1) = 500 + 400 = 900 \;\Rightarrow\; \text{Operand} = M[900] = 700 \end{aligned}$$

• Memory accesses for the operand: immediate 0, register direct 0, direct 1, register indirect 1, displacement 1, indirect 2.
• Trade-off to close the answer: speed falls and flexibility rises as we move from immediate (fastest) to indirect (slowest, but it can reach any address through a pointer).

2021 · Paper-II · Q2(b) · 5 marks

Q. The address field of an instruction has the decimal value 120. The machine uses register direct and register indirect addressing. Calculate the address of the corresponding operand.

Ans.

• Register direct: the field 120 names register R120. The operand is the content of R120 itself, so there is no memory address.
• Register indirect: the field 120 names register R120, whose content is the effective address. EA = (R120), and the operand is M[(R120)]. For example, if R120 held 2000, the operand would be at memory address 2000.

Equation form (taking $R120 = 2000$ and $M[2000] = 75$ as an illustration):

$$\begin{aligned} \text{Register direct:}\quad & \text{Operand} = (R120) = 2000 \quad \text{(no memory address)} \\ \text{Register indirect:}\quad & EA = (R120) = 2000 \;\Rightarrow\; \text{Operand} = M[2000] = 75 \end{aligned}$$

2021 · Paper-II · Q2(c) · 5 marks

Q. Compare the addressing modes of RISC and CISC machines. Give one example of addressing modes used in RISC and CISC respectively.

Ans.

• RISC: only a few simple modes: register, immediate and base + displacement (load/store only). Example: MIPS lw $t0, 8($s1).
• CISC: many complex modes: direct, indirect, indexed, auto-increment and decrement, scaled index. Example: x86 MOV EAX, [EBX + ESI*4 + 8].
• Effect: simple modes keep RISC decoding and pipelining easy, and complex modes make CISC programs shorter but slower to decode.

Effective-address examples in equation form:

• RISC (MIPS) lw $t0, 8($s1) (load word into register t0 from the address base register s1 + 8), with $s1 = 2000$:

$$EA = (s1) + 8 = 2000 + 8 = 2008$$

• CISC (x86) MOV EAX, [EBX + ESI*4 + 8] (copy into EAX the memory at base EBX + index ESI × 4 + displacement 8), with $EBX = 1000$ and $ESI = 5$:

$$EA = EBX + ESI \times 4 + 8 = 1000 + 20 + 8 = 1028$$

2025 · Paper-II · Q2(c)(i) · 5 marks

See the RISC versus CISC addressing-mode answer above (the same question as 2021 Q2(c)).