Memory Organization

CSS Optional — Paper-II, Section-A · Chapter 7 · 🔥 High-yield numerical topic

Memory organization studies how storage is arranged into a hierarchy, and how memory chips are physically interfaced with the CPU — the second part being one of the most reliably examined numerical areas.

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🗺️ Architecture Diagram — CPU to Memory-Chip Interfacing

graph TD
    CPU["CPU Address Bus - n bits"] --> LOW["Lower-order bits
to every chip in parallel"]
    CPU --> HIGH["Higher-order bits
to Decoder"]
    HIGH --> DEC{"Decoder"}
    DEC -->|CS0| CHIP0["Chip 0"]
    DEC -->|CS1| CHIP1["Chip 1"]
    DEC -->|CSn| CHIPN["Chip N"]
    LOW --> CHIP0
    LOW --> CHIP1
    LOW --> CHIPN

SECTION 1 — The Memory Hierarchy

┌─────────────┐   Fastest, smallest, costliest per bit
│  Registers  │   < 1 ns,  ~256 bytes
├─────────────┤
│  L1 Cache   │   ~1 ns,   32–64 KB
│  L2 Cache   │   ~4 ns,   256 KB–1 MB
│  L3 Cache   │   ~15 ns,  8–32 MB
├─────────────┤
│ Main Memory │   ~60–100 ns, 8–64 GB
│   (DRAM)    │
├─────────────┤
│  SSD / HDD  │   0.1 ms / 10 ms, TB range
├─────────────┤
│ Tape / Cloud│   seconds, unlimited
└─────────────┘   Slowest, largest, cheapest per bit

The governing principle: as you descend the hierarchy, capacity and cost-efficiency increase while speed decreases. The hierarchy works only because of locality of reference — see Cache Memory.

Inclusion property: data at any level is generally a subset of the level below it. Registers ⊂ L1 ⊂ L2 ⊂ Main Memory ⊂ Disk.

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SECTION 2 — Types of Memory

2.1 RAM (Random Access Memory) — volatile

Why DRAM needs refresh: a capacitor leaks charge, so its stored bit decays within milliseconds. Refresh circuitry periodically reads and rewrites every row. This refresh cycle is time during which the memory is unavailable — a genuine performance cost.

DRAM variants: SDRAM (synchronised to the bus clock) → DDR → DDR2/3/4/5, each generation roughly doubling the transfer rate per pin.

2.2 ROM (Read Only Memory) — non-volatile

• Mask ROM — programmed during manufacture; unchangeable.
• PROM — programmable once by the user (fuses blown permanently).
• EPROM — erasable by ultraviolet light; reusable.
• EEPROM — electrically erasable, byte by byte.
• Flash — electrically erasable in blocks; the basis of SSDs and USB drives.

Firmware/BIOS lives in ROM because the machine must find bootstrap code at power-on, before any disk is accessible.

2.3 Other Classifications

• Volatile vs non-volatile — whether contents survive power loss.
• Random access (RAM, ROM — any location in equal time) vs sequential access (tape) vs direct access (disk — a hybrid).
• Destructive vs non-destructive read — DRAM reads are destructive and require write-back; SRAM reads are not.
• Associative memory (CAM) — accessed by content rather than address; used in TLBs and fully associative caches.

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SECTION 3 — CPU–Memory Interfacing (Compatibility) ⭐

This is the section most often examined numerically. The question is always some form of: given a CPU with an n-bit address bus and an m-bit data bus, and memory chips of a certain organisation, how do we build the required memory system?

3.1 Memory Chip Notation

A memory chip is described as C × W:

C = number of addressable locations in the chip
W = word width (bits per location)

Example:  1K × 8  means  1,024 locations of 8 bits each  =  1 KB capacity
          4K × 4  means  4,096 locations of 4 bits each  =  2 KB capacity

Chip capacity (bits)  = C × W
Chip capacity (bytes) = (C × W) / 8

Address lines on the chip = log₂(C)
Data lines on the chip    = W

3.2 The Three Core Formulas

① Number of chips required = Required memory capacity / Capacity of one chip
                            (both expressed in bits, then simplify)

② Chips in PARALLEL   = Required word size / Chip word size
      → increases WORD WIDTH (horizontal expansion)

③ Chips in SERIES     = Required locations / Chip locations
      → increases NUMBER OF LOCATIONS (vertical expansion)

Total chips = Chips in parallel × Chips in series

3.3 Address Line Allocation ⭐

Total CPU address lines (n)     = log₂(Total addressable memory)

Lines going to each chip        = log₂(Locations per chip)   [lower-order lines]
Lines going to the DECODER      = n − (lines to chip)        [higher-order lines]

Number of chip-select outputs   = 2^(decoder lines)

Why this split matters: the lower-order address lines are wired in parallel to every chip and select a location within a chip. The higher-order lines feed a decoder whose outputs are the chip-select (CS) signals, choosing which chip responds. Getting this the right way round is the single most common failure point in these questions.

3.4 Memory Map and Address Range

Starting address of chip k = k × (Locations per chip)
Ending address of chip k   = Starting address + (Locations per chip − 1)

Addresses are conventionally written in hexadecimal.

3.5 CPU Capability Formulas

Maximum addressable memory = 2^(address bus width)     [byte-addressable]
Total capacity             = 2^n × (word size in bytes) [word-addressable]

Data transferred per access = Data bus width / 8  bytes

Memory bandwidth = (Data bus width / 8) × Memory bus frequency

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SECTION 4 — Solved Numericals

🧮 Numerical 1 — Basic Chip Count

Q: How many 1K × 8 RAM chips are needed to build a 16 KB memory system?

Step 1 — Capacity of one chip
    = 1K × 8 bits = 1,024 × 8 = 8,192 bits = 1 KB

Step 2 — Number of chips
    = Required / Per chip
    = 16 KB / 1 KB
    = 16 chips

Answer: 16 chips.

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🧮 Numerical 2 — Parallel and Series Expansion ⭐

Q: A CPU requires 16K × 16 memory. Available chips are 4K × 8. Determine the number of chips in parallel, in series, and the total.

Step 1 — Chips in PARALLEL (to widen the word)
    = Required word size / Chip word size
    = 16 bits / 8 bits
    = 2 chips in parallel

Step 2 — Chips in SERIES (to add locations)
    = Required locations / Chip locations
    = 16K / 4K
    = 4 chips in series

Step 3 — Total chips
    = Parallel × Series
    = 2 × 4
    = 8 chips

Answer: 2 in parallel, 4 in series, 8 chips total.

Verify by capacity:

Required = 16K × 16 = 16,384 × 16 = 262,144 bits
Per chip = 4K × 8   =  4,096 × 8  =  32,768 bits
Chips    = 262,144 / 32,768 = 8 ✓

Always run this cross-check — it catches arithmetic errors instantly.

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🧮 Numerical 3 — Address Line Allocation ⭐

Q: For the system in Numerical 2 (16K × 16 built from 4K × 8 chips), determine how the address lines are distributed.

Step 1 — Total address lines
    16K locations = 16,384 = 2¹⁴
    → CPU needs 14 address lines (A₀–A₁₃)

Step 2 — Lines to each chip (lower order)
    Each chip has 4K = 4,096 = 2¹² locations
    → 12 lines (A₀–A₁₁) go to every chip in parallel

Step 3 — Lines to the decoder (higher order)
    = 14 − 12 = 2 lines (A₁₂, A₁₃)

Step 4 — Decoder type
    2 input lines → 2² = 4 outputs
    → a 2-to-4 decoder, one chip-select per series bank

Answer: A₀–A₁₁ (12 lines) to the chips; A₁₂–A₁₃ (2 lines) to a 2-to-4 decoder generating 4 chip-select signals.

This matches the 4 series banks found in Numerical 2 ✓

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🧮 Numerical 4 — Complete Memory Map

Q: A system uses four 4K × 8 chips arranged in series to build 16 KB, starting at address 0000H. Give the address range of each chip in hexadecimal.

Locations per chip = 4K = 4,096 = 1000H

Chip 0 : 0000H  to  0FFFH
Chip 1 : 1000H  to  1FFFH
Chip 2 : 2000H  to  2FFFH
Chip 3 : 3000H  to  3FFFH

Working for Chip 1:

Start = 1 × 4096 = 4096 = 1000H
End   = 4096 + 4096 − 1 = 8191 = 1FFFH

Answer as tabulated above. Note each range ends at xFFFH because 4K = 1000H locations spans offsets 000H to FFFH.

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🧮 Numerical 5 — CPU–Memory Compatibility Check ⭐

Q: A CPU has a 20-bit address bus and a 16-bit data bus. (a) What is its maximum addressable memory? (b) How many 64K × 8 chips are required to fully populate that address space? (c) How are they arranged?

(a) Maximum addressable memory
    Locations = 2²⁰ = 1,048,576 locations
    Data bus  = 16 bits = 2 bytes per location
    Capacity  = 1,048,576 × 2 bytes = 2,097,152 bytes = 2 MB

(b) Required memory in bits = 1,048,576 × 16 = 16,777,216 bits
    Per chip                = 64K × 8 = 65,536 × 8 = 524,288 bits
    Chips required          = 16,777,216 / 524,288 = 32 chips

(c) Arrangement
    Parallel = 16 / 8   = 2 chips (to build the 16-bit word)
    Series   = 1M / 64K = 16 banks
    Total    = 2 × 16   = 32 chips ✓

Answer: (a) 2 MB, (b) 32 chips, (c) 2 in parallel × 16 in series.

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🧮 Numerical 6 — Decoder Sizing

Q: For the system in Numerical 5, determine the address line distribution and the decoder required.

Total address lines = 20 (A₀–A₁₉)

Lines to each chip  = log₂(64K) = log₂(65,536) = 16 lines (A₀–A₁₅)

Lines to decoder    = 20 − 16 = 4 lines (A₁₆–A₁₉)

Decoder outputs     = 2⁴ = 16 chip-select signals

Answer: A₀–A₁₅ to the chips; A₁₆–A₁₉ to a 4-to-16 decoder producing 16 chip-selects — exactly matching the 16 series banks ✓

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🧮 Numerical 7 — Mixed RAM and ROM System

Q: Design a memory system with 8 KB ROM and 24 KB RAM using 8K × 8 ROM chips and 8K × 8 RAM chips. Give the chip count and memory map starting at 0000H.

Step 1 — Chip counts
    ROM = 8 KB / 8 KB  = 1 chip
    RAM = 24 KB / 8 KB = 3 chips
    Total = 4 chips

Step 2 — Total address space
    8 KB + 24 KB = 32 KB = 2¹⁵  →  15 address lines (A₀–A₁₄)

Step 3 — Line allocation
    Per chip: 8K = 2¹³  →  13 lines (A₀–A₁₂)
    Decoder : 15 − 13 = 2 lines (A₁₃, A₁₄) → 2-to-4 decoder, 4 outputs ✓

Step 4 — Memory map (8K = 2000H per chip)
    ROM   : 0000H – 1FFFH
    RAM 1 : 2000H – 3FFFH
    RAM 2 : 4000H – 5FFFH
    RAM 3 : 6000H – 7FFFH

Answer as tabulated. ROM is placed at address 0000H because the CPU begins fetching from the reset vector at the bottom of the address space at power-on — a design point worth stating.

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🧮 Numerical 8 — Word-Addressable vs Byte-Addressable ⚠️

Q: A CPU has a 24-bit address bus. Find the total memory capacity if the machine is (a) byte-addressable, (b) word-addressable with a 32-bit word.

Locations = 2²⁴ = 16,777,216 locations

(a) Byte-addressable — 1 byte per location
    Capacity = 16,777,216 × 1 = 16,777,216 bytes = 16 MB

(b) Word-addressable — 32-bit (4-byte) word per location
    Capacity = 16,777,216 × 4 = 67,108,864 bytes = 64 MB

Answer: (a) 16 MB, (b) 64 MB.

⚠️ This is a deliberate exam trap. 2ⁿ always gives the number of locations, never automatically bytes. Read whether the machine is byte- or word-addressable before calculating.

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🧮 Numerical 9 — DRAM Refresh Overhead

Q: A DRAM chip has 4,096 rows and must refresh every row within 64 ms. Each refresh cycle takes 100 ns. What percentage of time is lost to refresh?

Step 1 — Total refresh time per 64 ms period
    = 4,096 rows × 100 ns
    = 409,600 ns
    = 0.4096 ms

Step 2 — Percentage overhead
    = 0.4096 / 64 × 100%
    = 0.64%

Answer: 0.64% of memory availability is lost to refresh. Small, but it is a cost SRAM does not pay at all — one reason cache uses SRAM.

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🧮 Numerical 10 — Memory Bandwidth and CPU Matching

Q: A CPU requests one 4-byte word every 2 ns. Main memory has a 64-bit data bus running at 200 MHz. Can memory keep up?

Step 1 — CPU demand
    = 4 bytes / 2 ns
    = 2 bytes/ns
    = 2 × 10⁹ bytes/sec
    = 2 GB/s

Step 2 — Memory supply
    = (64 / 8) bytes × 200 × 10⁶
    = 8 × 200,000,000
    = 1.6 × 10⁹ bytes/sec
    = 1.6 GB/s

Step 3 — Compare
    Demand 2 GB/s  >  Supply 1.6 GB/s

Answer: No — memory cannot keep up. There is a shortfall of 0.4 GB/s (20%).

Remedies to state in the answer: add cache to reduce the demand reaching main memory, widen the data bus, use DDR to double the transfer rate, or interleave memory banks. This "can it keep up?" framing is a favourite applied question.

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🧮 Numerical 11 — Memory Interleaving

Q: A memory system uses 4-way interleaving with a per-bank access time of 80 ns and a bus transfer time of 20 ns. How long does it take to read 4 consecutive words, and what is the speedup over non-interleaved memory?

Non-interleaved (sequential):
    = 4 × 80 = 320 ns

4-way interleaved (banks accessed in parallel, results transferred in sequence):
    = 80 (first access completes) + 3 × 20 (remaining transfers)
    = 80 + 60
    = 140 ns

Speedup = 320 / 140 = 2.29×

Answer: 140 ns, a 2.29× speedup. Interleaving exploits spatial locality by spreading consecutive addresses across banks so they can be accessed concurrently.

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SECTION 5 — Exam Guidance

🎯 CSS Exam Angle

Two things are examined here: the hierarchy diagram (a quick, reliable short question) and memory interfacing numericals (chip count, address lines, memory map), which are among the most repeated calculations in the paper.

For interfacing questions, follow this order every time and you cannot go wrong:

1. Capacity check — required bits ÷ chip bits = total chips.
2. Parallel = required word width ÷ chip word width.
3. Series = required locations ÷ chip locations.
4. Cross-verify parallel × series = total chips.
5. Address lines — lower-order to chips, higher-order to decoder.
6. Memory map in hexadecimal.

Always draw the block diagram showing the decoder feeding chip-select lines — it earns marks quickly and demonstrates you understand the wiring, not just the arithmetic.

🔁 Repeated CSS Questions

1. Draw and explain the memory hierarchy, noting the speed–cost trade-off at each level. (Frequently repeated)
2. Differentiate between SRAM and DRAM. (Very frequently repeated)
3. How many chips of size C × W are needed to build a memory of size X? Show the arrangement. (Numerical — frequently repeated)
4. Determine the address line distribution and decoder required for a given memory system. (Numerical)
5. Construct the memory map for a given chip arrangement in hexadecimal. (Numerical)
6. Differentiate between RAM and ROM, and describe the types of ROM.
7. Explain the principle of locality and why the memory hierarchy works.
8. Why does DRAM require refreshing while SRAM does not?
9. Explain memory interleaving and calculate the speedup it provides. (Numerical)
10. Determine whether a given memory system can sustain a given CPU's bandwidth demand. (Applied numerical)

⚠️ MCQ Traps

• Lower-order address lines go to the chips; higher-order lines go to the decoder. Reversing this is the most common error in interfacing questions.
• Parallel expansion widens the word; series expansion adds locations. Candidates routinely swap the two divisions.
• 2ⁿ gives the number of locations, not bytes. For a word-addressable machine, multiply by the word size (Numerical 8).
• SRAM does not need refresh; DRAM does. DRAM uses a capacitor that leaks charge.
• Cache uses SRAM; main memory uses DRAM. Never the reverse.
• DRAM reads are destructive and require automatic write-back; SRAM reads are non-destructive.
• ROM is non-volatile but not always unchangeable — EEPROM and Flash are rewritable ROM variants.
• Number of decoder outputs must equal the number of series banks. If they do not match, the arithmetic is wrong somewhere.
• Flash is erased in blocks, EEPROM byte by byte — the distinction that makes SSDs need garbage collection.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2017 · Paper-II · Q2(a) · 8 marks

Q. Discuss the following methods of storage systems: (i) direct access (ii) random access.

Ans.

• Direct access: units of data (blocks, sectors) have a unique physical address, and access is by a direct jump to the neighbourhood followed by a short sequential search. Access time varies with the location. Example: hard disk (move the head to the track, wait for the sector).
• Random access: every location has a unique, wired-in address and can be reached in the same time regardless of position and of the previous access. Example: RAM and ROM.
• Other methods: sequential (tape: data is reached in order) and associative (content-addressable memory: selected by stored content rather than by an explicit address).

Comparison and example (8-mark answer):

Illustration: To read an HDD sector, the drive may spend milliseconds positioning its head; to access RAM word 500, address decoding selects it without mechanically traversing earlier locations. Conclusion: Direct access is location-dependent, whereas random access is approximately location-independent. The eight-mark response should distinguish working principle, timing behavior, examples and applications rather than simply naming the terms.

2023 · Paper-II · Q2(a) · 7 marks

Q. Suggest reasons why RAMs traditionally have been organised as only one bit per chip whereas ROMs are usually organised with multiple bits per chip.

Ans.

• ROM is often a single chip holding the entire fixed program of a small system, so one chip must supply a whole word (such as 8 bits) on its own.
• RAM is built from many chips in parallel, with each chip supplying one bit of the word. The "one bit per chip" organisation makes the memory easy to scale to any word size and gives the most storage per package for a fixed number of pins (more address lines and a single data pin). A chip failure then damages only one bit of each word, which suits error-correcting codes.

2023 · Paper-II · Q2(b) · 7 marks

Q. A dynamic RAM must be refreshed 64 times per ms. Each refresh takes 150 ns, and a memory cycle takes 250 ns. What percentage of the memory's total operating time must be given to refreshes?

Ans.

• In 1 ms there are 64 refreshes × 150 ns = 9,600 ns.
• 1 ms = 1,000,000 ns.
• Percentage = 9,600 / 1,000,000 × 100 = 0.96%.
• (The 250 ns memory cycle is not needed for this calculation.)

2025 · Paper-II · Q4(b) · 10 marks

Q. What are the differences among sequential access, direct access and random access? Also explain the general relationship among access time, memory cost and capacity.

Ans.

• Relationships:
  • Faster access time → greater cost per bit.
  • Greater capacity → smaller cost per bit.
  • Greater capacity → slower access time.
• Memory hierarchy: to get both speed and size, systems use a small, fast, costly top (registers, cache) and a large, slow, cheap bottom (disk, tape).