Performance Metrics

CSS Optional — Paper-II, Section-A · Chapter 7 · 🔥 Guaranteed numerical topic

Every quantitative claim about a processor reduces to one equation. If you memorise nothing else from this chapter, memorise the CPU performance equation — most performance numericals in the paper are a rearrangement of it.

🗺️ Architecture Diagram — What Determines Performance

graph LR
    IC["Instruction Count
Program / Compiler / ISA"] --> T["Execution Time
T = IC x CPI x Cycle Time"]
    CPI["CPI
Organization / ISA"] --> T
    CT["Clock Cycle Time
Hardware Technology"] --> T
    T --> MIPS["MIPS = Clock Rate / CPI"]
    P["Parallel Fraction P"] --> AM["Amdahl's Law
Speedup = 1 / (1-P + P/S)"]
    S["Speedup Factor S"] --> AM

1. The Fundamental Confusion: Response Time vs Throughput

• Response time (execution time) — how long one task takes from start to finish. What a user cares about.
• Throughput — how many tasks complete per unit time. What a server operator cares about.

These are not the same and can move in opposite directions. Adding a second processor roughly doubles throughput but does not halve the response time of a single-threaded task. Examiners like this distinction because it exposes shallow preparation.

2. The CPU Performance Equation

$$\text{CPU Time} = IC \times CPI \times \text{Clock Cycle Time}$$

or

$$\text{CPU Time} = \frac{IC \times CPI}{\text{Clock Rate}}$$

The three factors are influenced by different things — a point worth stating in any performance answer:

This is why optimising one factor can worsen another: RISC lowers CPI but raises instruction count (see CISC vs RISC).

2A. CPI — All Formulas ⭐

CPI (Cycles Per Instruction) is the average number of clock cycles each instruction takes. Nearly every performance numerical in the paper uses one of the forms below.

Basic definitions

$$\text{①}\quad CPI = \frac{\text{Total clock cycles}}{\text{Total instruction count}}$$ $$\text{②}\quad \text{Total clock cycles} = IC \times CPI$$ $$\text{③}\quad CPI = \frac{\text{Execution time} \times \text{Clock rate}}{IC}$$ $$\text{④}\quad CPI = \frac{\text{Execution time}}{IC \times \text{Clock cycle time}}$$

Weighted / Average CPI (mixed instruction set)

When different instruction types take different numbers of cycles:

$$\text{⑤}\quad \text{Average } CPI = \frac{\sum (CPI_i \times Count_i)}{\sum Count_i}$$ $$\text{⑥}\quad \text{Average } CPI = \sum (CPI_i \times F_i)$$

where $F_i$ = fraction of instructions of type $i$, and $\sum F_i = 1$

Use ⑤ when the question gives counts, ⑥ when it gives percentages. They are the same equation.

IPC — the inverse

$$\text{⑦}\quad IPC = \frac{1}{CPI} \qquad CPI = \frac{1}{IPC}$$

Superscalar processors quote IPC because their CPI falls below 1 (more than one instruction completes per cycle). CPI = 0.5 means IPC = 2.

Effective CPI with stalls (memory, branches, hazards)

$$\text{⑧}\quad \text{Effective } CPI = \text{Base } CPI + \text{Stall cycles per instruction}$$ $$\text{⑨}\quad \text{Memory stalls} = \text{Accesses per instruction} \times \text{Miss rate} \times \text{Miss penalty}$$ $$\text{⑩}\quad \text{Branch stalls} = \text{Branch frequency} \times \text{Misprediction rate} \times \text{Misprediction penalty}$$ $$\text{⑪}\quad \text{Effective } CPI = \text{Base } CPI + \text{Memory stalls} + \text{Branch stalls} + \text{Other stalls}$$

CPI and MIPS

$$\text{⑫}\quad MIPS = \frac{\text{Clock rate}}{CPI \times 10^{6}}$$ $$\text{⑬}\quad CPI = \frac{\text{Clock rate}}{MIPS \times 10^{6}}$$

CPI-based speedup

$$\text{⑭}\quad \text{Speedup} = \frac{CPI_{old} \times \text{Cycle time}_{old}}{CPI_{new} \times \text{Cycle time}_{new}}$$

(valid when instruction count is unchanged)

Quick reference — what a CPI value tells you

Remember: lower CPI is better. More cycles per instruction means slower execution.

3. Clock Rate and Cycle Time

$$\text{Clock Cycle Time} = \frac{1}{\text{Clock Rate}}$$

• 1 GHz → cycle time = 1 ns
• 2 GHz → cycle time = 0.5 ns
• 4 GHz → cycle time = 0.25 ns

4. MIPS and Its Limitations

$$MIPS = \frac{IC}{\text{Execution Time} \times 10^{6}}$$

or

$$MIPS = \frac{\text{Clock Rate}}{CPI \times 10^{6}}$$

MIPS is an unreliable metric and examiners reward candidates who say so. It cannot be used to compare machines with different instruction sets, because one machine's instructions may do far more work than another's. A CISC machine at 100 MIPS may outperform a RISC machine at 200 MIPS. MIPS has been sardonically called "Meaningless Indicator of Processor Speed."

MFLOPS (millions of floating-point operations per second) is similarly limited for general workloads but meaningful for scientific computing.

5. Amdahl's Law (high-yield)

Amdahl's Law quantifies the limit on speedup when only part of a program can be improved.

$$\text{Speedup} = \frac{1}{(1 - P) + \frac{P}{S}}$$

where $P$ = fraction of execution time that is improvable/parallelizable, and $S$ = speedup factor applied to that fraction

Maximum theoretical speedup (as S → ∞):

$$\text{Max Speedup} = \frac{1}{1 - P}$$

The insight worth writing in an answer: the serial fraction is the hard ceiling. If 10% of a program cannot be parallelised, then no matter how many thousands of processors you add, the speedup can never exceed 10×. This is the fundamental argument against assuming that more cores always solve performance problems.

6. Speedup and Efficiency in Parallel Systems

$$S_p = \frac{\text{Time on 1 processor}}{\text{Time on } N \text{ processors}}$$ $$E = \frac{S_p}{N}$$

Efficiency of 1.0 (100%) means perfect linear scaling — rarely achieved because of communication overhead and the serial fraction.

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🧮 Solved Numerical 1 — Basic Execution Time

Q: A program has 10,000 instructions with an average CPI of 2, running on a 1 GHz processor. Find the execution time.

Given: $IC = 10{,}000$, $CPI = 2$, clock = 1 GHz

Solution:

$$\begin{aligned} \text{Cycle time} &= \frac{1}{1\ \text{GHz}} = 1\ \text{ns} \\ T &= IC \times CPI \times \text{Cycle time} \\ &= 10{,}000 \times 2 \times 1\ \text{ns} \\ &= 20{,}000\ \text{ns} = 20\ \mu\text{s} \end{aligned}$$

Answer: 20 μs.

🧮 Solved Numerical 2 — Mixed Instruction CPI (very common exam form)

Q: A program has the following instruction mix on a 2 GHz processor. Find the average CPI and total execution time.

Step 1 — Total cycles for each type:

$$\begin{aligned} \text{ALU} &= 50{,}000 \times 1 = 50{,}000 \\ \text{Load} &= 30{,}000 \times 4 = 120{,}000 \\ \text{Store} &= 10{,}000 \times 3 = 30{,}000 \\ \text{Branch} &= 10{,}000 \times 2 = 20{,}000 \\ \text{Total cycles} &= 220{,}000 \\ \text{Total instructions} &= 100{,}000 \end{aligned}$$

Step 2 — Average CPI:

$$CPI_{avg} = \frac{\text{Total cycles}}{\text{Total instructions}} = \frac{220{,}000}{100{,}000} = 2.2$$

Step 3 — Execution time (cycle time = 1/2 GHz = 0.5 ns):

$$T = 220{,}000 \times 0.5\ \text{ns} = 110{,}000\ \text{ns} = 110\ \mu\text{s}$$

Answer: Average CPI = 2.2, Execution time = 110 μs.

Insight for the examiner: Load instructions are only 30% of the count but consume 120,000/220,000 ≈ 55% of all cycles. This is why memory optimisation matters more than ALU optimisation — and it links directly to Cache Memory.

🧮 Solved Numerical 3 — Amdahl's Law (standard form)

Q: A program is 80% parallelizable and is run on 4 processors. Find the speedup and efficiency.

Given: $P = 0.8$, $S = N = 4$

Speedup:

$$\begin{aligned} \text{Speedup} &= \frac{1}{(1 - 0.8) + \frac{0.8}{4}} \\ &= \frac{1}{0.2 + 0.2} = \frac{1}{0.4} = 2.5\times \end{aligned}$$

Efficiency:

$$E = \frac{\text{Speedup}}{N} = \frac{2.5}{4} = 0.625 = 62.5\%$$

Answer: Speedup = 2.5×, Efficiency = 62.5%.

Note we used 4 processors but gained only 2.5× — the serial 20% is already dragging efficiency down to 62.5%.

🧮 Solved Numerical 4 — Amdahl's Ceiling

Q: For the same program (80% parallelizable), what is the maximum possible speedup with unlimited processors?

$$\begin{aligned} \text{Max Speedup} &= \frac{1}{1 - P} \\ &= \frac{1}{1 - 0.8} = \frac{1}{0.2} = 5\times \end{aligned}$$

Answer: 5×, no matter how many processors are added. Adding a million processors to an 80%-parallel program still yields under 5× — the definitive argument that parallel hardware alone cannot rescue a serial algorithm.

🧮 Solved Numerical 5 — Amdahl's Law Applied to a Component

Q: Floating-point operations account for 40% of a program's execution time. A new FPU makes them 5× faster. What is the overall speedup?

Given: $P = 0.4$, $S = 5$

Solution:

$$\begin{aligned} \text{Speedup} &= \frac{1}{(1 - 0.4) + \frac{0.4}{5}} \\ &= \frac{1}{0.6 + 0.08} = \frac{1}{0.68} \approx 1.47\times \end{aligned}$$

Answer: 1.47× overall. A 5× improvement to one component yields under 1.5× overall — the classic lesson: optimise the common case, not the fast case.

🧮 Solved Numerical 6 — Comparing Two Machines

Q: Machine A: 2 GHz, CPI = 1.5. Machine B: 3 GHz, CPI = 3. Both execute the same program with the same instruction count. Which is faster and by how much?

$$\begin{aligned} T_A &= IC \times 1.5 \times \frac{1}{2 \times 10^{9}} = IC \times 0.75\ \text{ns} \\ T_B &= IC \times 3.0 \times \frac{1}{3 \times 10^{9}} = IC \times 1.00\ \text{ns} \\ \frac{T_B}{T_A} &= \frac{1.00}{0.75} \approx 1.33 \end{aligned}$$

Answer: Machine A is 1.33× faster, despite its lower clock speed. This is the "megahertz myth" — a classic exam trap testing whether you know clock rate alone determines nothing.

🧮 Solved Numerical 6A — CPI from Percentages (form ⑥)

Q: A program has the following instruction mix given as percentages. Find the average CPI.

Step 1 — Verify fractions sum to 1:

$$0.45 + 0.25 + 0.15 + 0.15 = 1.00$$

Step 2 — Apply the weighted formula:

$$\begin{aligned} CPI_{avg} &= \sum (CPI_i \times F_i) \\ &= (1 \times 0.45) + (3 \times 0.25) + (2 \times 0.15) + (4 \times 0.15) \\ &= 0.45 + 0.75 + 0.30 + 0.60 \\ &= 2.10 \end{aligned}$$

Answer: Average CPI = 2.10.

Always verify the percentages total 100% before calculating — if they do not, you have misread the table.

🧮 Solved Numerical 6B — Effective CPI with Memory and Branch Stalls (forms ⑨–⑪)

Q: A processor has a base CPI of 1.0. 35% of instructions access memory. The cache miss rate is 4% with a 60-cycle miss penalty. 20% of instructions are branches, with a 10% misprediction rate and a 5-cycle penalty. Find the effective CPI.

Step 1 — Memory accesses per instruction (every instruction is fetched, plus 35% data accesses):

$$1.0 + 0.35 = 1.35$$

Step 2 — Memory stall cycles per instruction:

$$1.35 \times 0.04 \times 60 = 3.24\ \text{cycles}$$

Step 3 — Branch stall cycles per instruction:

$$0.20 \times 0.10 \times 5 = 0.10\ \text{cycles}$$

Step 4 — Effective CPI:

$$CPI_{eff} = 1.0 + 3.24 + 0.10 = 4.34$$

Answer: Effective CPI = 4.34.

Interpretation: the ideal CPI of 1.0 becomes 4.34 in practice — the processor runs 4.34× slower than its theoretical peak, and memory stalls account for 3.24 of the 3.34 added cycles (97%). Naming memory as the dominant bottleneck is the analytical point examiners reward.

🧮 Solved Numerical 6C — CPI and IPC Conversion (form ⑦)

Q: A superscalar processor completes 3.2 billion instructions per second at a clock rate of 1.6 GHz. Find its IPC and CPI.

$$IPC = \frac{\text{Instructions per second}}{\text{Clock rate}} = \frac{3.2 \times 10^{9}}{1.6 \times 10^{9}} = 2.0$$ $$CPI = \frac{1}{IPC} = \frac{1}{2.0} = 0.5$$

Answer: IPC = 2.0, CPI = 0.5.

A CPI below 1 is possible only on a superscalar processor issuing multiple instructions per cycle — a single-issue pipelined machine can at best reach CPI = 1.

🧮 Solved Numerical 6D — Finding CPI from Execution Time (form ③)

Q: A program of 800,000 instructions executes in 0.6 ms on a 2 GHz processor. Find the CPI.

$$\begin{aligned} CPI &= \frac{\text{Execution time} \times \text{Clock rate}}{IC} \\ &= \frac{0.6 \times 10^{-3} \times 2 \times 10^{9}}{800{,}000} \\ &= \frac{1{,}200{,}000}{800{,}000} = 1.5 \end{aligned}$$

Answer: CPI = 1.5.

Cross-check with the forward equation:

$$\begin{aligned} T &= IC \times CPI \times \text{Cycle time} \\ &= 800{,}000 \times 1.5 \times 0.5\ \text{ns} \\ &= 600{,}000\ \text{ns} = 0.6\ \text{ms} \end{aligned}$$

🧮 Solved Numerical 7 — MIPS Calculation

Q: A 2 GHz processor has an average CPI of 2.5. Calculate its MIPS rating.

$$\begin{aligned} MIPS &= \frac{\text{Clock Rate}}{CPI \times 10^{6}} \\ &= \frac{2 \times 10^{9}}{2.5 \times 10^{6}} = \frac{2000}{2.5} = 800 \end{aligned}$$

Answer: 800 MIPS — while noting in the exam that this figure is meaningless for cross-architecture comparison.

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🎯 CSS Exam Angle

Performance numericals appear in nearly every attempt, most often as Amdahl's Law or a mixed-instruction-mix CPI problem. A full-marks answer:

1. Writes the formula first, before substituting — partial marks are awarded for this alone.
2. Shows working line by line with units.
3. Boxes or bolds the final answer with its unit.
4. Adds a one-line interpretation ("adding processors cannot exceed 5× because 20% is serial"). This interpretive sentence is what separates a pass from a strong score.

🔁 Repeated CSS Questions

1. State Amdahl's Law and apply it to a numerical problem. (Very frequently repeated)
2. Given an instruction mix with per-type CPI values, calculate average CPI and execution time. (Numerical — frequently repeated)
3. Why is MIPS considered an unreliable measure of processor performance?
4. Differentiate between response time and throughput.
5. Compare two processors with different clock rates and CPI values. Which is faster? (Numerical)
6. Explain the three factors of the CPU performance equation and what determines each.
7. Define CPI and IPC. How are they related? (Frequently repeated)
8. Calculate the effective CPI of a processor accounting for cache misses and branch mispredictions. (Numerical)
9. Derive CPI given execution time, clock rate, and instruction count. (Numerical)

⚠️ MCQ Traps

• Higher CPI means a slower processor — more cycles are needed per instruction. Candidates often assume "higher = better."
• A higher clock rate does not guarantee better performance. Clock rate is only one of three factors (see Numerical 6).
• Amdahl's Law is limited by the serial fraction, not the parallel one. With P = 0.9, the ceiling is 10×, not 90×.
• MIPS cannot compare different instruction set architectures. Only meaningful within the same ISA family.
• In Amdahl's formula, S is the speedup applied to the improved fraction, which is usually — but not always — the number of processors. Read the question carefully.
• Efficiency falls as processors are added, even in a well-parallelised program.
• CPI below 1 requires a superscalar processor. A single-issue pipelined machine bottoms out at CPI = 1.
• CPI and IPC are reciprocals — CPI = 1/IPC. Lower CPI and higher IPC both mean better performance.
• Instruction fetch counts as a memory access. In effective-CPI problems use 1 + data-access fraction, not just the data fraction — omitting the fetch is the most common error here.
• Base CPI is the ideal, stall-free value. Effective CPI is always ≥ base CPI.

📜 Past-Paper Questions & MCQs (CSS 2016–2026)

2017 · Paper-II · Q2(b) · 6 marks

Q. If clock speed reaches its maximum, what are the two methods to increase the performance of a computer? Briefly explain.

Ans.

• 1. More parallelism: use multiple cores and multiprocessors, and deeper pipelines and superscalar execution, so more work is done per clock cycle.
• 2. Better architecture and memory: reduce CPI and memory delay by using larger and multi-level caches, faster memory, branch prediction, specialised hardware (GPU, accelerators) and a better instruction set.
• Why clock speed is limited: dynamic power is approximately P = αCV²f (activity factor α, switched capacitance C, voltage V, frequency f). Higher frequencies can require greater voltage and cooling, so frequency alone is not a sustainable performance strategy.
• Example: Four independent tasks on four cores can execute concurrently; alternatively, improved cache locality lowers memory-stall cycles even when clock frequency remains unchanged. More parallelism is limited by the serial fraction (Amdahl's law), and a larger cache does not always produce better performance.
• Six-mark conclusion: Improve work completed per cycle through parallel execution and reduce cycles lost per instruction through more efficient memory and processor organization.

2018 · Paper-I · Q2(e) · 2 marks

Q. Why do modern processors use more power when their clock frequency is increased?

Ans.

• Dynamic power is P = C·V²·f. Each clock tick charges and discharges the transistors, so more ticks per second mean more switching energy per second.
• A higher frequency usually also needs a higher supply voltage, and power grows with V², so in practice power rises roughly with the cube of frequency, producing heat.

Numerical example: the clock is raised from 2 GHz to 4 GHz and the supply voltage from 1.0 V to 1.2 V (same capacitance C):

$$\begin{aligned} \frac{P_2}{P_1} &= \left(\frac{V_2}{V_1}\right)^{2} \times \frac{f_2}{f_1} \\ &= \left(\frac{1.2}{1.0}\right)^{2} \times \frac{4}{2} \\ &= 1.44 \times 2 = 2.88 \end{aligned}$$

Doubling the clock raises the power by about 2.9 times.

2024 · Paper-II · Q2(b) · 7 marks

Q. How does the choice of architectural level impact the performance of a computer system? Give a numerical comparison between two architectural levels, highlighting strengths and weaknesses.

Ans.

• Architectural level is where a function is implemented: directly in hardware (digital logic), in microcode, or in software on top of the instruction set.

Numerical comparison 1 — a 32-bit multiply done at two levels (clock 1 GHz, software instructions take 1 cycle each):

Given: the hardware multiplier takes 3 cycles. The software shift-and-add routine loops 32 times, with 3 instructions per loop (test bit, add, shift).

$$\begin{aligned} T_c &= \frac{1}{1\ \text{GHz}} = 1\ \text{ns} \\ \text{Cycles}_{hw} &= 3 \\ \text{Cycles}_{sw} &= 32 \times 3 = 96 \\ T_{hw} &= 3 \times 1\ \text{ns} = 3\ \text{ns} \\ T_{sw} &= 96 \times 1\ \text{ns} = 96\ \text{ns} \approx 100\ \text{ns} \\ \text{Speed-up} &= \frac{T_{sw}}{T_{hw}} = \frac{96}{3} = 32 \end{aligned}$$

The hardware level is about 32 times faster. Summary of strengths and weaknesses:

Numerical comparison 2 — pipelined and non-pipelined execution ($n = 1{,}000$ instructions, $k = 5$ stages, stage time $t = 2\ \text{ns}$):

$$\begin{aligned} T_{\text{no pipe}} &= n \times k \times t = 1{,}000 \times 5 \times 2 = 10{,}000\ \text{ns} \\ T_{\text{pipe}} &= (k + n - 1) \times t = (5 + 1{,}000 - 1) \times 2 = 1{,}004 \times 2 = 2{,}008\ \text{ns} \\ \text{Speed-up} &= \frac{10{,}000}{2{,}008} = 4.98 \approx 5 \end{aligned}$$

The speed-up approaches the number of stages $k = 5$ as $n$ grows.

• Conclusion: lower levels (hardware) give speed, while higher levels (software) give flexibility and low cost.

2024 · Paper-II · Q2(c) · 6 marks

Q. A processor executes 1 billion instructions per second and has an instruction execution cycle of 4 cycles per instruction. Calculate the overall execution time for a program of 1 million instructions. Discuss how reducing the cycles per instruction affects performance.

Ans.

Given: $IC = 10^{6}$ instructions, $CPI = 4$, rating $= 10^{9}$ per second.

Assumption A — the 10⁹ is the clock rate (1 GHz). This is the reading that fits the second part of the question, because CPI then matters:

$$\begin{aligned} T_c &= \frac{1}{10^{9}} = 1\ \text{ns} \\ T &= IC \times CPI \times T_c \\ &= 10^{6} \times 4 \times 1\ \text{ns} \\ &= 4 \times 10^{6}\ \text{ns} = 4\ \text{ms} \end{aligned}$$

Assumption B — literal reading: 10⁹ instructions per second (the CPI is already inside this rate):

$$T = \frac{IC}{\text{Instruction rate}} = \frac{10^{6}}{10^{9}} = 10^{-3}\ \text{s} = 1\ \text{ms}$$

Here the clock would be $CPI \times 10^{9} = 4\ \text{GHz}$. State your assumption in the answer, because the working is what earns the marks.

Effect of reducing CPI (Assumption A, $T = 10^{6} \times CPI \times 1\ \text{ns}$ and $MIPS = \frac{10^{9}}{CPI \times 10^{6}}$):

$$\text{Speed-up} = \frac{CPI_{old}}{CPI_{new}} = \frac{4}{2} = 2$$

• With instruction count and clock fixed, execution time is directly proportional to CPI, so halving the CPI halves the time.
• CPI is reduced by pipelining, caches, branch prediction, superscalar issue and simpler instructions.
• The catch: simplifying instructions can raise the instruction count (as in RISC), so always judge by the full equation $T = IC \times CPI \times T_c$.

2025 · Paper-II · Q4(a) · 10 marks

Q. A 40 MHz processor runs a program of 100,000 instructions: integer arithmetic 45,000 (1 cycle), data transfer 32,000 (2 cycles), floating point 15,000 (2 cycles), control transfer 8,000 (2 cycles). Determine the effective CPI, MIPS rate and execution time.

Ans.

Given: $f = 40\ \text{MHz}$, $IC = 100{,}000$. Mix: integer arithmetic 45,000 (1 cycle), data transfer 32,000 (2 cycles), floating point 15,000 (2 cycles), control transfer 8,000 (2 cycles).

Required: effective CPI, MIPS rate and execution time.

Step 1 — Check the instruction total:

$$45{,}000 + 32{,}000 + 15{,}000 + 8{,}000 = 100{,}000 = IC$$

Step 2 — Cycles used by each type ($\text{cycles} = \text{count} \times CPI_i$):

$$\begin{aligned} \text{Integer arithmetic} &= 45{,}000 \times 1 = 45{,}000 \\ \text{Data transfer} &= 32{,}000 \times 2 = 64{,}000 \\ \text{Floating point} &= 15{,}000 \times 2 = 30{,}000 \\ \text{Control transfer} &= 8{,}000 \times 2 = 16{,}000 \\ \text{Total cycles} &= 155{,}000 \end{aligned}$$

Step 3 — Effective CPI:

$$CPI_{eff} = \frac{\text{Total cycles}}{IC} = \frac{155{,}000}{100{,}000} = 1.55$$

Cross-check with the fractions ($CPI = \sum CPI_i \times F_i$):

$$CPI_{eff} = (1 \times 0.45) + (2 \times 0.32) + (2 \times 0.15) + (2 \times 0.08) = 0.45 + 0.64 + 0.30 + 0.16 = 1.55$$

Step 4 — Cycle time:

$$T_c = \frac{1}{f} = \frac{1}{40 \times 10^{6}} = 25\ \text{ns}$$

Step 5 — Execution time:

$$\begin{aligned} T &= IC \times CPI_{eff} \times T_c \\ &= 100{,}000 \times 1.55 \times 25\ \text{ns} \\ &= 3{,}875{,}000\ \text{ns} = 3.875\ \text{ms} \end{aligned}$$

Step 6 — MIPS rate:

$$MIPS = \frac{f}{CPI_{eff} \times 10^{6}} = \frac{40 \times 10^{6}}{1.55 \times 10^{6}} = 25.81$$

Cross-check with the time:

$$MIPS = \frac{IC}{T \times 10^{6}} = \frac{100{,}000}{3.875 \times 10^{-3} \times 10^{6}} = \frac{100{,}000}{3{,}875} = 25.81$$

Answer: Effective CPI = 1.55, MIPS rate ≈ 25.8, Execution time = 3.875 ms.

MCQs

2025 P-II · Q3. If computer A executes a program in 10 seconds and computer B runs the same program in 15 seconds, how much faster is computer A than B?

• (A) 5.1 times
• (B) 1.4 times
• (C) 1 time
• (D) 1.5 times ✅
• Answer: (D) 1.5 times.
• Working:

$$\text{Speed-up} = \frac{T_B}{T_A} = \frac{15\ \text{s}}{10\ \text{s}} = 1.5$$ $$\frac{\text{Performance}_A}{\text{Performance}_B} = \frac{1/T_A}{1/T_B} = \frac{1/10}{1/15} = \frac{15}{10} = 1.5$$

• Why: performance is the reciprocal of execution time. The faster machine takes less time, so we divide the longer time by the shorter one. The wrong options come from dividing the other way round or from subtracting the times.

2025 P-II · Q4. A processor having a clock cycle of 0.25 ns will have a clock rate of:

• (A) 2 GHz
• (B) 3 GHz
• (C) 4 GHz ✅
• (D) 8 GHz
• Answer: (C) 4 GHz.
• Working:

$$\begin{aligned} f &= \frac{1}{T_c} = \frac{1}{0.25 \times 10^{-9}\ \text{s}} \\ &= 4 \times 10^{9}\ \text{Hz} = 4\ \text{GHz} \end{aligned}$$

• Why: frequency is the reciprocal of the period. Check with the table above: 0.25 ns is one quarter of 1 ns, so the rate is 4 times 1 GHz.