CPU Architecture

CSS Optional — Paper-II, Section-A · Chapter 7

The CPU is the component that fetches, decodes, and executes instructions. Understanding it means understanding three things: its functional units, its registers, and the datapath connecting them.

This page covers the CPU's internal structure. For classification of processor kinds (GPP, DSP, GPU, microcontroller), see Processor Types. For the step-by-step execution sequence, see Instruction Execution Cycle.

🗺️ Architecture Diagram — CPU Internal Structure

graph TD
    subgraph CPUBLOCK["CPU"]
        CU["Control Unit
decodes IR, issues signals"]
        ALU["ALU
arithmetic / logic / shift"]
        REG["Register File
PC, IR, ACC, SP, PSW, GPRs"]
        IB["Internal Bus"]
        MAR["MAR"]
        MBR["MBR"]
    end
    CU -->|control signals| ALU
    CU -->|control signals| REG
    REG <--> IB
    ALU <--> IB
    IB --> MAR
    IB --> MBR
    MAR -->|Address| ABUS["External Address Bus"]
    MBR <-->|Data| DBUS["External Data Bus"]
    ABUS --> MEM["Main Memory"]
    DBUS <--> MEM

1. The Three Functional Units

(a) Arithmetic Logic Unit (ALU)

Performs all computation:

• Arithmetic: add, subtract, multiply, divide, increment, decrement
• Logic: AND, OR, NOT, XOR
• Shift: left shift, right shift, rotate

The ALU is purely combinational — it has no memory of its own and simply transforms inputs into outputs. Its results set the flags (see below).

(b) Control Unit (CU)

The "conductor." It does not process data; it generates the control signals that tell every other unit what to do and when. It decodes the opcode in the IR and sequences the required micro-operations. Implemented as either hardwired logic or microprogrammed control — see Control Unit and Instruction Processing.

(c) Registers

Small, extremely fast storage inside the CPU, accessible in a single cycle. They sit at the very top of the memory hierarchy from Memory Organization.

2. CPU Registers ⭐ (highest-yield section)

Special-purpose registers

General-purpose registers (GPRs)

Used freely by the compiler for temporary values. RISC machines provide many (32+); CISC machines fewer (8–16). More GPRs mean fewer memory accesses — a key reason RISC achieves low CPI.

Status flags (in the PSW)

Conditional branch instructions work by testing these flags — this is how if statements become machine code.

3. Datapath and Buses

The datapath is the physical route data takes: from registers, through the ALU, and back to registers or memory. Internally the CPU has its own internal bus connecting registers to the ALU, distinct from the external system bus described in BUS.

The MAR/MBR pairing is worth understanding precisely: to read memory, the CPU places the address in MAR, asserts a Read control signal, and the memory system returns the value into MBR. MAR is thus the CPU's connection to the address bus, and MBR its connection to the data bus. This is why MAR's width equals the address bus width, and MBR's width equals the data bus width.

4. Instruction Set Architecture Styles

The number of explicit operands an instruction carries defines the machine's style:

• Zero-address (stack machine) — operands come implicitly from the stack: ADD (pops two, pushes result). Java bytecode works this way.
• One-address (accumulator machine) — one operand is implicitly the accumulator: ADD B means ACC ← ACC + B.
• Two-address — ADD A, B means A ← A + B; one operand is destroyed.
• Three-address — ADD A, B, C means A ← B + C; nothing is destroyed. Typical of RISC.

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🧮 Solved Numerical 1 — Register Widths

Q: A CPU has a 24-bit address bus and a 16-bit data bus. Determine the required widths of MAR and MBR, and the maximum addressable memory.

MAR width = address bus width = 24 bits
MBR width = data bus width    = 16 bits

Addressable memory = 2²⁴ = 16,777,216 locations = 16 MB (byte-addressable)

Answer: MAR = 24 bits, MBR = 16 bits, 16 MB addressable.

🧮 Solved Numerical 2 — Program Counter Behaviour

Q: A machine has fixed 4-byte instructions and is byte-addressable. If PC = 2000 before fetching an instruction, what is PC afterwards? What if the instruction is a jump to address 5000?

Normal sequential execution:
   PC_new = PC_old + instruction length
          = 2000 + 4 = 2004

Jump instruction executed:
   PC_new = 5000   (the jump overwrites the incremented value)

Answer: 2004 normally; 5000 after the jump.

Key sequencing point: the PC is incremented during the fetch stage, before the instruction executes. A jump therefore overwrites an already-incremented PC — which is exactly why the increment and the branch do not conflict.

🧮 Solved Numerical 3 — Flag Determination

Q: An 8-bit ALU computes 0111 1111 (+127) + 0000 0001 (+1). Determine the state of the Z, C, S, and V flags.

  0111 1111
+ 0000 0001
─────────────
  1000 0000

Result = 1000 0000, which in 2's complement is −128

Z (Zero)     = 0   → result is not zero
C (Carry)    = 0   → no carry out of the MSB
S (Sign)     = 1   → MSB is 1, result is negative
V (Overflow) = 1   → two positives were added and gave a negative

Answer: Z=0, C=0, S=1, V=1.

This example shows why carry and overflow are different flags: no carry occurred, yet a signed overflow did. (Full overflow rules in Arithmetic Microprocessor.)

🧮 Solved Numerical 4 — Register File Storage

Q: A RISC CPU has 32 general-purpose registers, each 64 bits wide. How much total storage does the register file provide?

Total bits  = 32 × 64 = 2,048 bits
Total bytes = 2,048 / 8 = 256 bytes

Answer: 256 bytes. Strikingly small — yet this quarter-kilobyte handles the overwhelming majority of a program's data accesses, which is exactly why register count so strongly affects performance.

🧮 Solved Numerical 5 — Instruction Format Bit Allocation

Q: A 32-bit instruction format must support 64 distinct operations and address 32 general-purpose registers in a three-address format. How many bits remain unused or available for immediate values?

Opcode field       = log₂(64) = 6 bits
Register field × 3 = 3 × log₂(32) = 3 × 5 = 15 bits
                                    ──────────────
Used                                = 21 bits

Remaining = 32 − 21 = 11 bits

Answer: 11 bits remain — typically used for an immediate value, shift amount, or function-code extension. (This is essentially the MIPS R-type instruction layout.)

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🎯 CSS Exam Angle

Register identification is a reliable MCQ source, and the CPU block diagram is a common short question. Draw the diagram showing ALU, CU, register file, and the internal bus, with MAR/MBR bridging to the external address and data buses — labelled diagrams earn marks quickly.

The strongest answers explain why each register exists rather than merely listing them: the PC exists to maintain sequential flow, the IR to hold the instruction stable while the CU decodes it, MAR/MBR to interface with two physically distinct buses.

🔁 Repeated CSS Questions

1. List and explain the functions of the major CPU registers. (Very frequently repeated)
2. Draw and explain a CPU block diagram showing the ALU, control unit, and registers.
3. Differentiate between PC and IR. (MCQ favourite)
4. What is the role of MAR and MBR in a memory read operation?
5. Explain the CPU status flags and their role in conditional branching.
6. Differentiate between zero-address, one-address, two-address, and three-address instruction formats.

⚠️ MCQ Traps

• PC holds the address of the NEXT instruction; IR holds the CURRENT instruction itself. Note also that PC holds an address while IR holds the instruction. This pair is the single most-tested distinction on this page.
• MAR holds an address; MBR holds data. Their widths differ because they connect to different buses.
• Carry flag ≠ Overflow flag. Carry concerns unsigned arithmetic; overflow concerns signed arithmetic. They can be set independently (see Numerical 3).
• The ALU does not store anything — it is combinational logic. Storage is the registers' job.
• The Control Unit does not process data; it only generates control signals.
• The Stack Pointer is essential to function calls — return addresses are pushed onto the stack, which is why recursion depth is limited by stack size.