4. Computer Organization & Architecture — Computer Science

FPSC CSS Computer Science past papers (2016–2026) — 54 questions: 9 MCQs, 45 subjective parts. Newest first.

Part A — Subjective Questions

2026 · Paper-I · Q2(c) (8 marks)

Question

Your office plans to upgrade hardware but employees don't know what components matter. Which computer hardware components would you explain to help them choose better systems?

Solution

Key hardware components to explain when choosing/upgrading a computer:

CPU (Processor): the 'brain' of the computer; its clock speed, number of cores/threads, and cache size determine how fast tasks and multitasking are handled — critical for compute-heavy work.
RAM (Main Memory): temporary working memory used while programs run; more RAM allows more applications/larger datasets to run smoothly without slowdown from disk swapping.
Storage (SSD vs HDD): SSDs are far faster (quicker boot/app load times) than traditional HDDs, though HDDs offer more capacity per rupee/dollar; SSD capacity and type (SATA vs NVMe) affect overall system responsiveness.
Motherboard: determines compatibility between the CPU, RAM, storage and expansion cards, and how easily the system can be upgraded later.
GPU (Graphics Card): important for graphics-intensive work (design, video editing, gaming, AI/ML workloads); integrated graphics suffice for basic office tasks.
Power Supply Unit (PSU): must supply adequate, stable wattage for all components, especially if a discrete GPU is added.
Cooling system: keeps components within safe operating temperatures, especially under sustained heavy load.
Ports/Connectivity: USB, HDMI, Ethernet/Wi-Fi standards affecting peripheral and network compatibility.

Explaining these lets employees match hardware choices to their actual workload (e.g., prioritizing RAM and SSD for office productivity, CPU and GPU for design/engineering work) rather than upgrading arbitrarily.

2025 · Paper-I · Q2(b) (6 marks)

Question

Provide a comparison of different data storage devices in terms of speed, size, access time and cost.

Solution

Storage devices form a memory hierarchy that trades speed for capacity and cost:

CPU Registers: fastest (sub-nanosecond access), extremely small (bytes/words), highest cost per bit; hold data being actively processed.
Cache (SRAM): very fast (1-10 ns access), small (KB-MB), high cost per bit; buffers between CPU and RAM.
Main Memory (DRAM/RAM): fast (tens of ns), moderate size (GBs), moderate cost, volatile working memory for running programs.
SSD (flash): microsecond-level access, large capacity (hundreds of GB to TBs), moderate cost per GB, non-volatile, no moving parts, faster than HDD.
HDD (magnetic disk): millisecond access (limited by seek time and rotational latency), very large capacity (TBs), lowest cost per GB among common secondary storage, non-volatile.
Optical disks (CD/DVD/Blu-ray): slow access (hundreds of ms), limited capacity (GBs), cheap per disk, mainly for distribution/archival.
Magnetic tape: slowest, sequential-only access (seconds to minutes), extremely high capacity, cheapest per byte, used for long-term backup/archiving.

General rule: moving from registers to tape, access time increases, storage capacity increases, and cost per byte decreases — the classic speed–capacity–cost trade-off underlying the memory hierarchy.

2025 · Paper-II · Q2(a) (3 marks)

Question

An instruction requires five stages to execute: Stage-1 (instruction fetch) requires = 30 ns Stage-2 (instruction decode) = 9 ns Stage-3 (instruction execute) = 20 ns Stage-4 (Memory access) = 35 ns Stage-5 (Store results) = 10 ns An instruction must proceed through the stages in sequence. What is the minimum asynchronous time for any single instruction to complete?

Solution

Without pipelining (asynchronous, non-overlapped execution), a single instruction must pass through all five stages one after another, so the minimum time to complete one instruction is simply the sum of all stage times: Total time = 30 + 9 + 20 + 35 + 10 = 104 ns. So the minimum asynchronous completion time for any single instruction is 104 ns.

2025 · Paper-II · Q2(b) (7 marks)

Question

Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes, and a hit ratio of H = 0.95. Main memory uses a block transfer capability that has a firstword (4 bytes) access time of 50 ns and an access time of 5 ns for each word thereafter. (i) What is the access time when there is a cache miss? Assume that the cache waits until the line has been fetched from main memory and then re-executes for a hit. (3) (ii) Suppose that increasing the line size to 128 bytes increases the H to 0.97. Does this reduce the average memory access time? (4)

Solution

(i) Miss access time: A 64-byte line = 16 words of 4 bytes each. Memory fetch time = first word (50 ns) + remaining 15 words x 5 ns = 50 + 75 = 125 ns. On a miss, the cache first spends 2.5 ns discovering the miss, then waits for the 125 ns line fetch, then re-executes the access as a hit (another 2.5 ns). Miss access time = 2.5 + 125 + 2.5 = 130 ns.

(ii) With a 128-byte line = 32 words: memory fetch time = 50 + (31 x 5) = 50 + 155 = 205 ns. New miss access time = 2.5 + 205 + 2.5 = 210 ns.

Average access time = H x (cache hit time) + (1-H) x (miss access time):

Original (64B, H=0.95): Tavg = 0.95(2.5) + 0.05(130) = 2.375 + 6.5 = 8.875 ns
New (128B, H=0.97): Tavg = 0.97(2.5) + 0.03(210) = 2.425 + 6.3 = 8.725 ns

Since 8.725 ns < 8.875 ns, YES — increasing the line size to 128 bytes (raising H to 0.97) slightly reduces the average memory access time, even though each individual miss now costs more (210 ns vs 130 ns), because misses become proportionally rarer.

2025 · Paper-II · Q2(c) (10 marks)

Question

(i) Compare the set of addressing modes of RISC and CISC machines. Give one example of addressing modes used in RISC and CISC respectively. (5) (ii) Explain Parallel Processing, and also draw pipeline processing for instruction: Ai*Bi+Ci (5)

Solution

(i) RISC vs CISC addressing modes: RISC architectures deliberately support very few, simple addressing modes (typically only register and register + small immediate offset for load/store instructions), because only load/store instructions touch memory and all arithmetic works on registers — this keeps instruction decode/execution simple and fast, one cycle per instruction on average. Example (RISC, e.g., MIPS/ARM): LOAD R1, 4(R2) — base register + displacement addressing, used only by load/store. CISC architectures support many rich, complex addressing modes (direct, indirect, indexed, base+index+displacement, auto-increment/decrement, etc.) because arithmetic instructions themselves can operate directly on memory operands, reducing code size at the cost of more complex, multi-cycle decode/execution hardware. Example (CISC, e.g., x86): ADD EAX, [EBX+ECX*4+8] — a single instruction combining base, index, scale and displacement addressing directly in an arithmetic operation.

(ii) Parallel processing is the simultaneous use of multiple processing resources (functional units, cores, or pipeline stages) to execute parts of a computation at the same time rather than strictly sequentially, in order to increase throughput. Pipeline processing for AiBi+Ci: this expression naturally splits into independent stages that can be pipelined: S1: Fetch Ai, Bi, Ci S2: Multiply — compute AiBi S3: Add — compute (AiBi)+Ci In a pipelined arithmetic unit, while S3 is adding Ci to the product of the (i)-th pair, S2 can simultaneously be multiplying the (i+1)-th pair, and S1 can be fetching the (i+2)-th operands — so for a stream of i=1..n pairs, after an initial fill latency of 3 stage-times, one final result (AiBi+Ci) is produced every single stage-time, giving much higher throughput than doing each triplet fully sequentially.

2025 · Paper-II · Q4(a) (10 marks)

Question

A benchmark program is run on a 40 MHz processor. The executed program consists of 100,000 instruction executions, with the following instruction mix and clock cycle count: Instruction Type | Instruction Count | Cycles per Instruction Integer arithmetic | 45,000 | 1 Data transfer | 32,000 | 2 Floating point | 15,000 | 2 Control transfer | 8000 | 2 Determine the effective CPI, MIPS rate, and execution time for this program.

Solution

Total clock cycles = sum of (instruction count x cycles per instruction) for each type: = (45,000 x 1) + (32,000 x 2) + (15,000 x 2) + (8,000 x 2) = 45,000 + 64,000 + 30,000 + 16,000 = 155,000 cycles.

Total instructions executed = 45,000 + 32,000 + 15,000 + 8,000 = 100,000 instructions.

Effective CPI = Total cycles / Total instructions = 155,000 / 100,000 = 1.55 cycles/instruction.

Execution time = Total cycles / Clock rate = 155,000 / (40 x 10^6 Hz) = 0.003875 s = 3.875 ms.

MIPS rate = Clock rate / (CPI x 10^6) = (40 x 10^6) / (1.55 x 10^6) = 40 / 1.55 ≈ 25.81 MIPS. (Equivalently: MIPS = Instruction count / (Execution time x 10^6) = 100,000 / (0.003875 x 10^6) ≈ 25.81 MIPS.)

Results: Effective CPI ≈ 1.55, Execution time = 3.875 ms, MIPS rate ≈ 25.81.

2025 · Paper-II · Q4(b) (10 marks)

Question

What are the differences among sequential access, direct access, and random access? Also, write and explain the general relationship among access time, memory cost, and capacity.

Solution

Sequential access: to reach a desired location, the device must read through all preceding locations in order starting from the beginning (or current position) — access time depends heavily on the location's position in the sequence. Example: magnetic tape.

Direct access: individual records/blocks have a unique address and the read/write head can jump directly to the general vicinity of the desired block, then perform a limited sequential search/wait within that block (e.g., waiting for disk rotation). Access time depends partly on location but is much less variable than pure sequential access. Example: magnetic/optical disk (seek to track/cylinder, then rotational search).

Random access: any location can be accessed directly in an essentially constant, equal amount of time regardless of the sequence of prior accesses or the physical location of the data. Example: main memory (RAM), cache.

General relationship among access time, cost, and capacity: as one moves up the memory hierarchy from tape/disk (slow, cheap per bit, huge capacity) through main memory (moderate speed/cost/capacity) to cache and registers (fastest, most expensive per bit, smallest capacity), access time decreases while cost per bit increases, and capacity decreases. In other words: faster memory technologies cost more per bit and are therefore provided in smaller quantities, while slower technologies are cheap enough per bit to be deployed in very large capacities — this trade-off is precisely why computer systems use a layered memory hierarchy (registers → cache → RAM → SSD/HDD → tape) instead of one uniform memory type, to approximate the speed of the fastest technology at a cost close to the cheapest one.

2024 · Paper-II · Q2(a) (7 marks)

Question

Why are multi-processor systems considered advantageous in computer architecture? How does parallel processing fundamentally improve the performance and scalability of a computer system?

Solution

Multi-processor systems are advantageous because they allow multiple instruction streams/processes to execute simultaneously rather than one at a time, increasing overall system throughput, improving responsiveness for multitasking workloads, and providing fault tolerance/redundancy (if one processor fails, others can continue operating).

Parallel processing fundamentally improves performance by dividing a large workload into independent sub-tasks that execute concurrently on separate processors/cores, reducing total wall-clock completion time (subject to the fraction of the workload that can actually be parallelized, per Amdahl's Law). It improves scalability because, unlike a single processor which has a hard physical limit on clock speed (constrained by power/heat), a multi-processor system can handle growing workloads simply by adding more processing units, allowing performance to scale roughly with the number of processors for well-parallelized problems - something a single, faster processor design cannot sustainably achieve.

2024 · Paper-II · Q2(b) (7 marks)

Question

How does the choice of architectural level impact the performance of a computer system? Provide a numerical comparison between two different architectural levels, highlighting their strengths and weaknesses.

Solution

The architectural level - e.g., choosing a CISC (Complex Instruction Set Computer) vs. RISC (Reduced Instruction Set Computer) design - directly affects performance because it determines both the number of instructions needed to accomplish a task and the average number of clock cycles each instruction requires (CPI, cycles per instruction). Overall time is governed by: Execution Time = Instruction Count x CPI x Clock Cycle Time.

Numerical example: suppose a memory-to-memory add can be done by a CISC processor in just 2 complex instructions, but each instruction (being complex, microcoded) takes an average CPI of 4, giving total cycles = 2 x 4 = 8 cycles. A RISC processor might need 4 simple instructions (load, load, add, store) for the same task, but each takes CPI = 1, giving total cycles = 4 x 1 = 4 cycles. Despite executing MORE instructions, the RISC design finishes in fewer total cycles because of its much lower CPI - illustrating that architectural-level choices (instruction complexity vs. cycle efficiency) can matter more for performance than raw instruction count alone. CISC's strength is code density/fewer instructions (useful when memory was scarce); RISC's strength is simpler, faster, more pipeline-friendly execution, which is why RISC principles now dominate modern high-performance and mobile processors.

2024 · Paper-II · Q2(c) (6 marks)

Question

If a processor executes 1 billion instructions per second and has an instruction execution cycle of 4 cycles per instruction. Calculate the overall execution time for a program with 1 million instructions. Discuss how reducing the number of cycles per instruction can impact performance.

Solution

The processor's instruction throughput is given directly as 1 billion (10^9) instructions per second.

Execution time for 1 million (10^6) instructions = Instruction Count / Instruction rate = 10^6 / 10^9 seconds = 10^-3 seconds = 1 millisecond.

(For reference, since CPI = 4, the underlying clock frequency = instruction rate x CPI = 10^9 x 4 = 4 GHz.)

Impact of reducing CPI: if the clock frequency stays fixed at 4 GHz but CPI is reduced (e.g., to 2 cycles/instruction through better pipelining), the instruction throughput would double to 2 billion instructions/sec, halving the execution time for the same 1-million-instruction program to 0.5 milliseconds. This shows that, per the fundamental performance equation (Time = Instruction Count x CPI / Clock Rate), lowering CPI - through techniques like pipelining, superscalar execution, or simpler instructions - directly and proportionally improves performance for a fixed clock speed and instruction count.

2024 · Paper-II · Q3(a) (7 marks)

Question

Why cache memory is considered a critical component in a computer system? How does the internal and external data representation contribute to optimizing memory usage and system efficiency?

Solution

Cache memory is critical because there is a large speed gap between the very fast CPU and much slower main memory (DRAM); cache, being small but very fast (SRAM), bridges this gap by exploiting the principle of locality of reference (temporal locality - recently used data is likely reused soon; spatial locality - nearby data is likely accessed soon), keeping frequently/recently used data close to the CPU. This dramatically reduces the average memory access time without the prohibitive cost of making all of main memory as fast as cache.

Internal data representation (how the CPU/registers hold data - fixed word sizes, binary encoding) must be efficiently mapped to external representation (how data is laid out in memory/cache - byte-addressable storage, cache line structure). Because cache is organized in fixed-size lines/blocks holding several contiguous words, a consistent, compact data representation lets multiple related data items be packed into a single cache line, so that fetching one line brings in several useful values at once (exploiting spatial locality) and avoids wasted cache capacity from mismatched or padded representations - directly improving both memory usage efficiency and overall system performance.

2024 · Paper-II · Q3(b) (7 marks)

Question

Explain the concept of parallelism in computer architecture. How does the internal structure of a microprocessor contribute to parallel processing capabilities?

Solution

Parallelism in computer architecture means performing multiple computational operations simultaneously rather than strictly one after another, and it exists at several levels: instruction-level parallelism (executing multiple instructions concurrently via pipelining or superscalar issue), data-level parallelism (applying the same operation to multiple data elements at once via SIMD/vector units), and thread/task-level parallelism (running independent threads concurrently on multiple cores or via simultaneous multithreading).

The internal structure of a modern microprocessor is specifically designed to exploit these forms: a pipelined datapath overlaps the fetch/decode/execute stages of successive instructions; superscalar processors contain multiple redundant functional units (ALUs, FPUs) so more than one instruction can be issued and executed per cycle; wide SIMD registers/execution units let a single instruction operate on several data values simultaneously; and multiple physical cores on a single chip allow entirely separate instruction streams (threads/processes) to execute truly concurrently. Together, these internal architectural features are what translate the theoretical opportunity for parallelism in a program into actual, realized performance gains.

2024 · Paper-II · Q3(c) (6 marks)

Question

Break down the stages of the instruction execution cycle in a computer system. How do the characteristics of CISC and RISC architectures influence the execution cycle?

Solution

The classic instruction execution cycle consists of these stages:

Fetch: retrieve the next instruction from memory, using the Program Counter (PC) to locate it.
Decode: interpret the instruction's opcode and identify its operands/addressing modes.
Execute: perform the actual operation (e.g., an ALU computation).
Memory access: read from or write to memory, if the instruction requires it.
Write-back: store the result of the operation into a register.

CISC architectures use complex, variable-length instructions that may internally combine several of these stages (e.g., a single instruction might read from memory, compute, and write back memory directly), executed via microcode over multiple clock cycles per instruction (higher CPI), which can blur the boundary between execute and memory-access stages.

RISC architectures use simple, fixed-length, single-cycle-per-stage instructions, cleanly separating the five stages into a straightforward, highly pipelined datapath (the classic 5-stage RISC pipeline: IF-ID-EX-MEM-WB), achieving CPI close to 1 and enabling higher clock speeds, at the cost of needing more instructions overall (since each instruction does less work) - relying on the compiler to generate the needed sequences rather than complex hardware decoding.

2023 · Paper-I · Q2(a) (8 marks)

Question

Write a detailed note on any 03 Super Computing Technologies being used in the world. List key characteristics in each case.

Solution

Massively Parallel Processing (MPP) systems: thousands of independent processing nodes, each with its own memory, connected via a high-speed interconnect, working together on a single large problem by dividing it into communicating sub-tasks. Key characteristics: linear scalability by adding nodes, distributed-memory architecture, requires message-passing programming models (e.g., MPI).
GPU-accelerated computing: uses Graphics Processing Units with thousands of simple cores optimized for data-parallel workloads alongside traditional CPUs, exploited heavily in modern supercomputers (e.g., systems using NVIDIA GPUs). Key characteristics: extremely high throughput for parallel/vector operations, energy-efficient FLOPS-per-watt compared to CPU-only systems, widely used for AI/ML and scientific simulation.
Cluster computing: a supercomputer built from many commodity servers (nodes) connected by a fast network (e.g., InfiniBand), managed as a single coordinated resource via job schedulers. Key characteristics: cost-effective (built from off-the-shelf hardware), flexible/scalable, requires fault-tolerant software since node failures are common at scale.

(Other valid examples include vector processors and quantum computing prototypes.)

2023 · Paper-I · Q2(b) (6 marks)

Question

What performance metrics are used to analyze the capacity of Super Computers? Discuss.

Solution

Key performance metrics for supercomputers include:

FLOPS (Floating Point Operations Per Second): the primary raw compute-power metric, measured via benchmarks like LINPACK (used to rank systems on the TOP500 list), often expressed in petaFLOPS or exaFLOPS.
Memory bandwidth and latency: how fast data can move between memory and processing units, often a bottleneck for data-intensive workloads.
Interconnect bandwidth/latency: speed of communication between nodes, critical for parallel workloads with heavy inter-node communication.
Scalability: how performance grows as more nodes/cores are added (measured via speedup and efficiency, related to Amdahl's Law).
Power efficiency (FLOPS per watt): increasingly important given the enormous energy consumption of supercomputers (tracked by the Green500 list).
Storage I/O throughput: rate of reading/writing large datasets to persistent storage.

2023 · Paper-II · Q2(a) (7 marks)

Question

Suggest reasons why RAMs traditionally have been organized as only one bit per chip whereas ROMs are usually organized with multiple bits per chip.

Solution

RAM chips need to pack an extremely large number of storage cells at minimum cost per bit; the most area/cost-efficient internal layout for a RAM chip is a large, dense square array of simple memory cells addressed by a row and a column decoder, which naturally yields exactly one bit of output per access for a given row/column address - keeping the read/write circuitry, sense amplifiers, and refresh logic (for DRAM) as simple as possible per chip while maximizing bit density and minimizing the number of pins needed for data.

ROM chips, in contrast, are usually much smaller in total capacity and are typically used to hold complete words (e.g., microcode, lookup tables, firmware) that are always read out together; since ROM only needs address-decoding logic (no write circuitry, sense amplifiers for write, or refresh logic), it is comparatively cheap to widen the output, so manufacturers commonly organize ROM chips with multiple output bits per chip - reducing the number of chips needed to build a full memory word and matching ROM's typical role of supplying a complete word per access.

2023 · Paper-II · Q2(b) (7 marks)

Question

Consider a dynamic RAM that must be given a refresh cycle 64 times per ms. Each refresh operation requires 150 ns; a memory cycle requires 250 ns. What percentage of the memory's total operating time must be given to refreshes?

Solution

Total refresh time per millisecond = 64 refreshes x 150 ns = 9,600 ns.

Total available time in 1 millisecond = 1 ms = 1,000,000 ns.

Percentage of time spent on refreshing = (9,600 / 1,000,000) x 100% = 0.96%.

So only 0.96% of the memory's total operating time needs to be devoted to refresh operations, leaving the remaining 99.04% available for normal memory read/write cycles (each of which takes 250 ns).

2023 · Paper-II · Q2(c) (6 marks)

Question

In the context of RAID, what is the distinction between parallel access and independent access?

Solution

Parallel access RAID organizations (e.g., RAID 2 and RAID 3) stripe each individual block of data at the bit or byte level across ALL the disks in the array; therefore, every single I/O request from the host involves all disks operating in parallel simultaneously to service that one request. This delivers very high data-transfer rate for a single large sequential transfer, but only one I/O request can be serviced by the whole array at a time.

Independent access RAID organizations (e.g., RAID 1, RAID 4, RAID 5, RAID 6) stripe data at the level of whole blocks/stripes rather than bits, so that each member disk can, in principle, operate independently and service a different I/O request concurrently. This allows multiple separate I/O requests to be handled in parallel by different disks, which is far better suited to transaction-processing workloads with many small, concurrent requests, whereas parallel access arrays are better suited to a single very large, high-throughput transfer.

2023 · Paper-II · Q4(a) (12 marks)

Question

A 32-bit computer has two selector channels and one multiplexor channel. Each selector channel supports two magnetic disk and two magnetic tape units. The multiplexor channel has two line printers, two card readers, and ten VDTs terminals connected to it. Assume the following transfer rates: Disk drive 800 Kbytes/s, Magnetic tape drive 200 Kbytes/s, Line printer 6.6 Kbytes/s, Card Reader 1.2 Kbytes/s, VDT 1 Kbytes/s. Estimate the maximum aggregate I/O transfer rate in this system.

Solution

A selector channel serves only ONE of its attached devices at full speed at any given instant (it is dedicated to a single high-speed device transfer at a time), so each selector channel contributes at most the rate of its single fastest attached device - here the disk drive at 800 KB/s (faster than the 200 KB/s tape drive). With two selector channels operating simultaneously (on two different device transfers), their combined contribution is: 2 x 800 KB/s = 1600 KB/s.

The multiplexor channel, by contrast, interleaves (byte-multiplexes) data from ALL its attached slow devices simultaneously, so its contribution is the SUM of all its attached devices' rates: 2 line printers x 6.6 KB/s = 13.2 KB/s 2 card readers x 1.2 KB/s = 2.4 KB/s 10 VDTs x 1 KB/s = 10 KB/s Multiplexor channel total = 13.2 + 2.4 + 10 = 25.6 KB/s

Maximum aggregate I/O transfer rate = selector channels + multiplexor channel = 1600 + 25.6 = 1625.6 KB/s (approximately 1.63 MB/s).

2023 · Paper-II · Q5(c) (5 marks)

Question

What is the distinction between instruction-level parallelism and machine parallelism?

Solution

Instruction-Level Parallelism (ILP) is a measure inherent to the PROGRAM/instruction stream itself: it reflects the degree to which the instructions in a piece of code are independent of one another (free of data/control dependencies) and could, in principle, be executed simultaneously or out of order without changing the program's result.

Machine parallelism is a measure inherent to the HARDWARE: it reflects the processor's actual ability to exploit that available ILP in practice - i.e., how many instructions the machine can fetch, decode, issue, and execute concurrently, determined by factors such as the number of pipelines/functional units, issue width, and out-of-order execution capability.

In short: ILP describes the opportunity for parallelism present in the code, while machine parallelism describes the hardware's capacity to actually take advantage of that opportunity - a program with high ILP still runs sequentially on a simple, low-machine-parallelism processor.

2022 · Paper-II · Q4(a) (8 marks)

Question

Assume a pipeline with four stages: fetch instruction (FI), decode instruction and calculate addresses (DA), fetch operand (FO), and execute (EX). Draw a diagram for a sequence of 7 instructions, in which the third instruction is a branch that is taken and in which there are no data dependencies.

Solution

With no data dependencies, instructions 1 and 2 flow through the pipeline normally. Instruction 3 is a branch; its outcome (taken) is only known after its EX stage. Because of this, the instructions fetched in the cycles immediately after the branch (following the sequential path) are fetched speculatively and must be discarded (flushed) once the branch is found to be taken; the correct target instruction can only be fetched once EX of the branch completes.

Cycle: 1 2 3 4 5 6 7 8 9 10 I1: FI DA FO EX I2: FI DA FO EX I3 (branch): FI DA FO EX I4 (wrong path): FI DA FO (flushed) I5 (wrong path): FI DA (flushed) I4' (target): FI DA FO EX I5': FI DA FO EX I6: FI DA FO EX I7: FI DA FO EX

Since the branch resolves at the end of its EX stage (cycle 6), the fetches attempted in cycles 4, 5 and 6 along the wrong (fall-through) path are discarded, producing a 3-cycle penalty (bubble) before the correct target instruction (I4') can begin fetching in cycle 7. The total time to complete all 7 instructions is therefore extended by this branch penalty compared to the no-branch ideal case.

2022 · Paper-II · Q4(b) (6 marks)

Question

A set associative cache consists of 64 lines, or slots, divided into 4-slot sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.

Solution

Number of sets = total lines / lines per set = 64 / 4 = 16 sets, so the set index needs log2(16) = 4 bits.

Word offset within a block: block size = 128 words, so the offset needs log2(128) = 7 bits.

Total number of blocks in main memory = 4K = 4096 = 2^12, so the block-identifying part of the address (tag + set index together) needs 12 bits; since 4 bits are used for the set index, the tag field needs 12 - 4 = 8 bits.

Main memory address format (total 8+4+7 = 19 bits): | Tag (8 bits) | Set index (4 bits) | Word offset (7 bits) |

When an address is presented, the set index selects one of the 16 sets, the tag is compared against the tags of the (up to 4) lines in that set to check for a hit, and the word offset selects the specific word within the matched block.

2022 · Paper-II · Q4(c) (6 marks)

Question

Why is DMA access to main memory given higher priority than CPU access to main memory?

Solution

DMA (Direct Memory Access) is used to transfer data directly between an I/O device and main memory at the device's real-time speed, without CPU intervention for every word. I/O devices (disks, network cards) operate on strict timing: if the DMA controller does not get access to the memory bus promptly when new data is ready (e.g., a disk block streaming in, or a network packet arriving), that data can be lost, corrupted, or an overrun/underrun condition can occur, because the device hardware cannot simply pause and wait.

The CPU, on the other hand, can tolerate a short delay in accessing memory - it may stall for a few cycles (or work from cache/pipeline buffers) without any loss of correctness, since its operations are not tied to an external real-time data stream. Therefore, giving DMA controllers higher priority for the memory bus ensures I/O data integrity and keeps peripheral throughput matching hardware speeds, at the (acceptable) cost of occasionally delaying the CPU by a memory cycle or two - a scheme sometimes called "cycle stealing".

2021 · Paper-II · Q2(a) (10 marks)

Question

The addressing in a typical instruction format are done by using different addressing modes. Examine any five addressing modes with an example based on the contents of address field, actual address and contents of memory location.

Solution

Five addressing modes:

Immediate: the address field itself contains the actual OPERAND (not an address). Example: address field = 5 → operand used directly = 5 (no memory reference at all).
Direct: the address field contains the effective address (EA) of the operand in memory. Example: address field = 200 → EA = 200 → operand = Memory[200] (e.g. Memory[200] = 25, so operand = 25).
Indirect: the address field contains the address of a memory location which itself holds the effective address of the operand. Example: address field = 200 → Memory[200] = 350 (this is the actual address) → operand = Memory[350] (e.g. = 25).
Register: the address field specifies a register that holds the operand directly (no memory access at all). Example: address field = R1 → operand = contents of R1 directly (e.g. R1 = 25).
Register Indirect: the address field specifies a register whose CONTENTS is the effective address of the operand in memory. Example: address field = R1, R1 = 200 → EA = 200 → operand = Memory[200] (e.g. = 25).

2021 · Paper-II · Q2(b) (5 marks)

Question

The decimal value of address field in an instruction is 120. The addressing mode of the machine's architecture is register direct and register indirect addressing. Calculate the address of corresponding operand.

Solution

Register Direct mode: the address field (120) itself designates register R120, and the OPERAND is the content of that register directly — there is no separate memory address computed at all; the effective address is simply 'register R120' (EA = R120, operand = contents of R120). Register Indirect mode: the address field (120) again designates register R120, but this time R120 holds the ADDRESS of the operand in main memory, not the operand itself. So the effective address of the operand is EA = [R120] (i.e. whatever value is currently stored inside register R120), and the actual operand is then Memory[EA] = Memory[contents of R120]. Since the numeric content of R120 was not given, the address of the operand is expressed symbolically as EA = Content(R120).

2021 · Paper-II · Q2(c) (5 marks)

Question

Compare the set of addressing modes of RISC and CISC machines. Give one example of addressing modes used in RISC and CISC respectively.

Solution

CISC machines support a rich, large set of addressing modes to allow complex operations within a single instruction — immediate, direct, indirect, register, register indirect, indexed, base+displacement, base+index+scale+displacement, relative, and auto-increment/decrement — since CISC instructions are permitted to operate directly on memory operands. RISC machines deliberately restrict addressing modes to just a very small set — typically only Immediate and Register modes for most instructions, plus a single simple Base+Offset (Register + displacement) mode used exclusively by the load/store instructions, since RISC's load/store architecture means only load and store instructions ever touch memory at all. Example: x86 (CISC) supports a complex mode like MOV EAX, [EBX + ECX*4 + 8] (base + scaled index + displacement) in a single instruction. ARM/MIPS (RISC) uses only simple base+offset addressing for memory access, e.g. LW R1, 8(R2) (load the word at address R2+8 into R1), with all other operations working purely on registers.

2020 · Paper-II · Q2(a) (7 marks)

Question

Explain Moore's law. List high computing requirements in contemporary computing.

Solution

Moore's Law is an observation made by Intel co-founder Gordon Moore in 1965 that the number of transistors that can be economically fabricated on an integrated circuit doubles approximately every two years, while the cost per transistor falls correspondingly — leading to exponential growth in computing power and density over time. It is an empirical trend, not a physical law, and its pace has slowed in recent years as transistor sizes approach atomic scales. High computing requirements in contemporary computing include: training large deep-learning/AI models (requiring massive parallel GPU/TPU compute), big-data analytics over massive datasets, real-time video/image/speech processing, large-scale scientific simulation (climate modelling, genomics, drug discovery), cryptocurrency/blockchain computation, cloud-scale data-centre workloads serving millions of concurrent users, and high-throughput 5G/IoT data processing — all of which increasingly rely on massive parallelism, specialized accelerators (GPUs/TPUs), and high memory bandwidth rather than single-core clock-speed growth alone, since Moore's Law-driven single-thread gains have slowed.

2020 · Paper-II · Q2(b) (6 marks)

Question

List and briefly define two approaches to dealing with multiple interrupts.

Solution

Disable interrupts while processing an interrupt (sequential/non-nested handling): when the processor is servicing one interrupt, it ignores or defers all further interrupts until the current handler finishes. This is simple to implement, but time-critical interrupts arriving during a long handler may be delayed or lost, reducing responsiveness.
Define priorities for interrupts (nested interrupt handling): interrupts are assigned priority levels, and a higher-priority interrupt is allowed to PREEMPT the handler currently servicing a lower-priority interrupt. This provides faster response to urgent/critical events at the cost of added complexity — the system must manage nested execution contexts and stack frames correctly.

2020 · Paper-II · Q2(c) (7 marks)

Question

What is instruction-level parallelism? What are some typical distinguishing characteristics of RISC organization?

Solution

Instruction-Level Parallelism (ILP) is the potential for overlapping or simultaneously executing multiple machine instructions within a single program by exploiting independence between them, using techniques such as pipelining, superscalar (multiple-issue) execution, out-of-order execution, speculative execution, and branch prediction. Typical RISC (Reduced Instruction Set Computer) characteristics: a small set of simple, fixed-length instructions; a strict load/store architecture (only load/store instructions access memory, all other operations work on registers); a large, uniform set of general-purpose registers; most instructions execute in a single clock cycle; a hardwired (not microprogrammed) control unit; few addressing modes; and heavy reliance on compiler-level optimisation (e.g. instruction scheduling) rather than complex hardware — all of which make RISC instructions especially well-suited to deep pipelining and exploiting ILP.

2019 · Paper-II · Q2(a) (8 marks)

Question

Compare the main features of CISC and RISC architectures. Which type of architecture is suitable for pipelining?

Solution

CISC (Complex Instruction Set Computer): large, variable-length instructions; many addressing modes; instructions can directly operate on memory; complex, often microprogrammed control unit; fewer general-purpose registers; a single instruction may take multiple clock cycles; smaller compiled code size (e.g. x86). RISC (Reduced Instruction Set Computer): small, simple, fixed-length instructions; few addressing modes; strict load/store architecture (only load/store instructions touch memory, all others operate on registers); hardwired control unit; large uniform register set; most instructions execute in a single clock cycle; larger code size but simpler, faster execution (e.g. ARM, MIPS). RISC is far more suitable for pipelining, because its fixed-length, uniform-format, single-cycle instructions flow through a pipeline's stages (fetch/decode/execute/memory/writeback) predictably and without the variable timing and complex micro-op decoding that CISC's variable-length, variable-cycle instructions introduce, which causes pipeline stalls and hazards.

2019 · Paper-II · Q2(b) (6 marks)

Question

Demonstrate use of superscalar approach to achieve instruction level parallelism using a suitable example.

Solution

A superscalar processor contains multiple parallel execution units (e.g. two ALUs, a load/store unit, and a floating-point unit) and can fetch, decode and issue more than one instruction per clock cycle, dispatching independent instructions to whichever unit is free. Example: consider the sequence

I1: ADD R1, R2, R3   ; integer addition
I2: MUL F1, F2, F3   ; floating-point multiply
I3: SUB R4, R1, R5   ; integer subtraction (depends on I1)

A dual-issue superscalar processor can dispatch I1 (to the integer ALU) and I2 (to the FPU) in the SAME clock cycle because they use different execution units and have no data dependency between them. I3, however, must wait until I1 completes because it depends on R1. This ability to detect independent instructions and execute them concurrently across multiple functional units — rather than waiting for one instruction to finish before starting the next — is exactly how superscalar design exploits instruction-level parallelism (ILP).

2019 · Paper-II · Q2(c) (6 marks)

Question

List all basic functions of buses in the context of computer architecture.

Solution

A bus is a shared communication pathway connecting the CPU, memory, and I/O devices. Its basic functions:

Data transfer — the data bus carries the actual data/instructions being moved between CPU, memory and I/O.
Addressing — the (unidirectional) address bus carries the memory or I/O port address that identifies the source/destination of a transfer.
Control/timing signals — the control bus carries signals such as read/write, memory/IO select, clock, interrupt requests and acknowledgements, that coordinate and synchronise all transfers.
Bus arbitration — determines which device is allowed to act as bus master when multiple devices want to use the bus simultaneously (bus request/bus grant signals).
Power distribution — in many physical bus standards, some lines also supply electrical power to connected devices.

2018 · Paper-I · Q2(e) (2 marks)

Question

Why do modern processors use more power when their clock frequency is increased?

Solution

Dynamic power consumption in a CMOS processor is approximately P = C * V^2 * f, where C is capacitance, V is supply voltage, and f is clock frequency. Increasing frequency directly increases power roughly linearly (more switching events per second, each dissipating energy). Additionally, achieving a higher stable clock frequency typically requires a higher supply voltage as well, and since power depends on V^2, even a modest voltage increase causes a much larger power increase. This combined frequency-and-voltage scaling is why modern processors consume disproportionately more power (and generate more heat) at higher clock speeds, which is precisely why chip makers hit a 'power wall' and shifted toward multi-core designs instead of ever-higher clock speeds.

2018 · Paper-II · Q2(A) (8 marks)

Question

Briefly describe the functionality of the following CPU special-purpose registers: Instruction Register (IR), Memory Data Register (MDR) and Program Counter (PC).

Solution

Instruction Register (IR): holds the instruction currently being decoded and executed by the CPU. After an instruction is fetched from memory, it is placed into the IR, from which the Control Unit extracts and interprets the opcode and operand fields to determine what operation to perform.

Memory Data Register (MDR) (also called Memory Buffer Register, MBR): temporarily holds the data being transferred to or from main memory - during a memory read, it holds the value just fetched from memory (which is then typically copied to the IR if it's an instruction, or to a general register if it's data); during a memory write, it holds the value about to be written to the address in the MAR.

Program Counter (PC) (also called Instruction Pointer): holds the memory address of the NEXT instruction to be fetched and executed. After each instruction fetch, the PC is automatically incremented to point to the following instruction (unless a jump/branch/call instruction explicitly loads a new address into the PC, altering the normal sequential flow of execution).

2018 · Paper-II · Q2(B) (6 marks)

Question

Differentiate between Address, Data and Control bus.

Solution

Address Bus: a unidirectional bus that carries the memory address (or I/O port address) that the CPU wants to read from or write to. Its width (number of lines) determines the maximum addressable memory size (e.g. a 32-bit address bus can address up to 2^32 locations). Only the CPU drives this bus (it flows one way: CPU to memory/devices).

Data Bus: a bidirectional bus that carries the actual data being transferred between the CPU, memory, and I/O devices. Its width determines how many bits can be transferred in one bus cycle (e.g. a 64-bit data bus transfers 64 bits at once). Data flows in both directions - CPU to memory (write) and memory to CPU (read).

Control Bus: carries control and timing signals that coordinate and synchronize activities between the CPU, memory, and I/O devices - e.g. Read/Write signals, clock signals, interrupt request/acknowledge lines, bus request/grant signals, and reset signals. It is not a single unified bidirectional data path like the other two, but rather a collection of individual control lines, each carrying a specific signal, some driven by the CPU and some by other devices.

Together these three buses form the system bus that allows the CPU to communicate with all other components of the computer.

2018 · Paper-II · Q2(C) (6 marks)

Question

Discuss instruction pipelining in the context of fetch-decode-execute cycle.

Solution

Instruction pipelining is a technique that overlaps the execution of multiple instructions by dividing the basic fetch-decode-execute cycle into distinct, sequential stages, and allowing different instructions to be at different stages simultaneously - much like an assembly line.

A simple pipeline might have stages: Fetch (F) -> Decode (D) -> Execute (E) -> Write-back (W).

Without pipelining, each instruction must fully complete all stages before the next instruction's fetch begins, so the CPU is idle during much of each stage for other potential work. With pipelining, while instruction 1 is in its Execute stage, instruction 2 can simultaneously be in its Decode stage, and instruction 3 can simultaneously be in its Fetch stage:

Cycle: 1 2 3 4 5 Instr1: F D E W Instr2: F D E W Instr3: F D E W

This means that although any single instruction still takes the same total latency (4 cycles here) to fully complete, the overall THROUGHPUT improves dramatically - ideally, one instruction completes every clock cycle once the pipeline is full, ideally achieving up to a 4x speedup with a 4-stage pipeline.

Pipelining is limited by hazards: structural hazards (hardware resource conflicts), data hazards (an instruction needs a result from an instruction still in the pipeline ahead of it), and control hazards (branch instructions disrupt the assumed sequential fetch order, requiring pipeline flushes or branch prediction).

2017 · Paper-I · Q2(b) (6 marks)

Question

Describe the difference between Harvard and Von-Neumann architectures of computers. Also discuss their traits in the light of their capabilities.

Solution

Von Neumann architecture: uses a single, shared memory space and a single bus for both instructions and data. The CPU cannot fetch an instruction and access data simultaneously since both travel over the same bus - this is known as the 'Von Neumann bottleneck'. It is simpler and cheaper to design, and is the basis of most general-purpose computers (PCs, servers) because a single unified memory is flexible (memory can be dynamically apportioned between code and data).

Harvard architecture: uses physically separate memories and buses for instructions and data, allowing the CPU to fetch an instruction and read/write data at the same time, improving throughput/speed and enabling better pipelining. It is more complex/costly and less flexible (fixed program and data memory sizes), which is why it is mainly used in specialized systems like microcontrollers, DSPs (Digital Signal Processors), and embedded systems where speed and predictability matter more than general flexibility.

In practice, many modern CPUs use a 'modified Harvard architecture' - separate L1 instruction and data caches (for speed, like Harvard) backed by a single unified main memory (like Von Neumann) - combining the benefits of both.

2017 · Paper-I · Q8(c) (5 marks)

Question

Write short notes on any FOUR of the following (5 each): (c) Parallel processing and the use of pipelining for this purpose

Solution

Parallel processing is the simultaneous execution of multiple computations/instructions, using multiple processing units (multiple cores/processors) to increase overall throughput and reduce total execution time for suitable (decomposable) workloads. It contrasts with sequential (one-instruction-at-a-time) execution.

Pipelining is a specific technique for achieving instruction-level parallelism within a single processor: the execution of an instruction is broken into several discrete stages (e.g. Fetch, Decode, Execute, Memory access, Write-back), and while one instruction is in its Execute stage, the next instruction can simultaneously be in its Decode stage, and the one after that in its Fetch stage - like an assembly line. This overlapping means that although any single instruction still takes the same total time to complete, the overall instruction throughput (instructions completed per clock cycle) is greatly increased, ideally approaching one instruction completed per clock cycle once the pipeline is full.

Challenges (hazards) that reduce pipelining efficiency: structural hazards (resource conflicts), data hazards (an instruction needs a result not yet produced by an earlier instruction still in the pipeline), and control hazards (branch instructions that change the flow, causing fetched-ahead instructions to be discarded/flushed).

2017 · Paper-II · Q2(b) (6 marks)

Question

If clock speed reaches its maximum then what are the two methods to increase the performance of a computer? Briefly explain.

Solution

Once clock speed (frequency) cannot be increased further (due to power/heat limits, the 'power wall'), two main methods increase performance instead:

Parallelism (multi-core processing): instead of making a single core faster, add multiple processing cores on the same chip that can execute multiple instruction streams/threads/processes simultaneously. This increases overall throughput for workloads that can be split into independent, concurrently-executable tasks, without needing higher clock frequency, and keeps power/heat manageable since each core can run at a modest frequency.
Improving Instructions Per Cycle (IPC) / architectural efficiency: redesign the processor's microarchitecture to do more useful work per clock cycle rather than more cycles per second - e.g. deeper/smarter pipelining, superscalar execution (issuing multiple instructions per cycle), out-of-order execution, better branch prediction, larger/faster caches to reduce memory-stall cycles, and wider SIMD/vector units for data-parallel operations.

Both approaches raise effective performance without raising the clock frequency itself, which is why the industry shifted from the historical 'megahertz race' toward multi-core CPUs and micro-architectural improvements from the mid-2000s onward.

2017 · Paper-II · Q2(c) (6 marks)

Question

Draw and explain instruction execution state diagram with interrupt.

Solution

Instruction cycle with interrupt handling (state diagram):

[ Fetch ] --> [ Execute ] --> [ Check for Interrupt ] | -----------------+----------------- | No interrupt pending | Interrupt pending v v (loop back to Fetch) [ Interrupt Handling ] | 1. Save current process state/PC (context) 2. Load address of Interrupt Service Routine (ISR) 3. Execute the ISR 4. Restore saved state/PC | v (return to Fetch, resume interrupted instruction stream)

Explanation: after every Execute stage, the CPU checks whether an interrupt request (from I/O devices, timers, or exceptions) is pending. If none, it proceeds directly to fetch the next instruction as normal. If an interrupt is pending, the CPU suspends the current instruction sequence, saves enough state (Program Counter and relevant registers, typically onto the stack) to resume later, transfers control to the appropriate Interrupt Service Routine (found via an interrupt vector table), executes it, then restores the saved state and resumes normal fetch-execute processing exactly where it left off. This mechanism allows the CPU to respond promptly to asynchronous events (e.g. keyboard input, disk completion) without continuously polling devices.

2017 · Paper-II · Q5(a) (8 marks)

Question

Explain the functionality and purposes of following registers with diagrams: (i) Memory Address Register (MAR) (ii) Memory Buffer Register (MBR) (iii) Instruction Register (IR)

Solution

Memory Address Register (MAR): holds the memory address of the data/instruction that is about to be fetched from, or written to, memory. Before any memory access, the CPU places the target address into the MAR, which is then sent out on the address bus to memory. Diagram: [CPU internal bus] -> [MAR] -> (Address Bus) -> [Memory]

Memory Buffer Register (MBR) (also called Memory Data Register, MDR): temporarily holds the data being transferred to or from memory - during a read, it receives the data fetched from the address in MAR; during a write, it holds the data to be sent to that address. Diagram: [Memory] <-> (Data Bus) <-> [MBR] <-> [CPU internal bus / other registers]

Instruction Register (IR): holds the current instruction that has just been fetched from memory (via MBR) and is being decoded/executed by the Control Unit. The Control Unit reads the opcode from the IR to determine which operation the CPU must perform next. Diagram: [MBR] -> [IR] -> [Control Unit] -> (control signals to ALU/registers)

Together: to fetch an instruction, the Program Counter's value is copied into MAR, memory places the instruction at that address onto the data bus into MBR, and the CPU then copies MBR's contents into IR for decoding - this is the essential hardware mechanism underlying the fetch stage of the instruction cycle.

2016 · Paper-I · Q3(b) (6 marks)

Question

Explain and differentiate between volatile and non-volatile memory, giving examples.

Solution

Volatile memory requires continuous power to retain its stored data; the moment power is switched off, its contents are lost. It is fast, used for temporary working storage while a program executes. Examples: RAM (DRAM, SRAM), CPU cache and CPU registers.

Non-volatile memory retains its contents even when power is removed, making it suitable for permanent/long-term storage. It is generally slower to access than volatile memory. Examples: ROM, Flash memory (SSD, USB drives, memory cards), magnetic hard disks, and optical disks (CD/DVD).

Key differences:

Persistence: volatile loses data on power-off; non-volatile keeps it.
Speed: volatile (RAM) is much faster than non-volatile secondary storage.
Cost per byte: volatile memory is more expensive per unit than non-volatile secondary storage.
Use: volatile memory holds the currently running program and data; non-volatile memory holds the operating system, files, and programs when the machine is off, and is used for backup/permanent storage.

2016 · Paper-II · Q3(a) (8 marks)

Question

RAID is a physical disk drives viewed by the operating system as a single logical drive, where data are distributed across the physical drives of an array. Explain different levels of RAID? Elaborate your answer with suitable diagrams.

Solution

RAID (Redundant Array of Independent Disks) combines multiple physical disks into one logical unit for performance and/or fault tolerance.

RAID 0 (Striping): data split into blocks striped across all disks, no redundancy. Best performance, but a single disk failure loses all data. [Disk1: A1,A3][Disk2: A2,A4]
RAID 1 (Mirroring): data is duplicated identically on two (or more) disks. Excellent fault tolerance (survives one disk failure) but only 50% storage efficiency. [Disk1: A1,A2][Disk2: A1,A2] (mirror copy)
RAID 2: bit-level striping with Hamming-code error correction stored on dedicated disks; rarely used commercially.
RAID 3: byte-level striping with a single dedicated parity disk.
RAID 4: block-level striping with a single dedicated parity disk; parity disk becomes a bottleneck for writes.
RAID 5: block-level striping with parity distributed across all disks (no single dedicated parity disk); tolerates one disk failure; good balance of performance, capacity efficiency and fault tolerance - the most commonly used level. [Disk1: A1,A2,P3][Disk2: A2... wait] Diagram: [D1: A1, B1, P] [D2: A2, P, C1] [D3: P, B2, C2] (parity P rotates across disks)
RAID 6: like RAID 5 but with two independent parity blocks distributed across disks; tolerates two simultaneous disk failures.
RAID 10 (1+0): a stripe of mirrors - combines mirroring (RAID 1) and striping (RAID 0) for both performance and fault tolerance, at the cost of using only half the raw disk capacity.

2016 · Paper-II · Q3(b) (6 marks)

Question

The basic function performed by a computer is execution of a program, which consists of set of instructions stored in memory. The processor required for a single instruction is called an instruction cycle. Elaborate basic instruction cycle used by modern computer systems. Also add diagrams for explanation.

Solution

The Instruction Cycle (fetch-decode-execute cycle) is the sequence of steps the CPU repeats for every machine instruction:

Fetch: the CPU reads the instruction pointed to by the Program Counter (PC) from memory into the Instruction Register (IR); PC is then incremented to point to the next instruction.
Decode: the Control Unit interprets the opcode in the IR to determine which operation is to be performed and which operands/registers are involved.
Fetch Operands (if needed): any required operands are fetched from registers or memory.
Execute: the ALU (or other functional unit) performs the actual operation (arithmetic, logic, data movement, or a branch).
Store/Write-back: the result, if any, is written back to a register or memory.
Check for interrupts: the CPU checks if an interrupt is pending before beginning the next fetch.

Diagram (cycle): PC -> [FETCH instruction from Memory into IR] -> [DECODE opcode] -> [FETCH operands] -> [EXECUTE in ALU] -> [STORE result] -> [check interrupts] --loop back to FETCH-->

This cycle repeats continuously as long as the CPU is running, forming the basic execution model of the Von Neumann architecture.

2016 · Paper-II · Q3(c) (6 marks)

Question

Differentiate between Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) architectures.

Solution

RISC (Reduced Instruction Set Computer):

Small set of simple, fixed-length instructions, each executing in (close to) one clock cycle.
Fewer addressing modes; load/store architecture - only LOAD/STORE instructions access memory, all other operations work on registers.
Relies heavily on the compiler to combine simple instructions to perform complex tasks.
Larger number of general-purpose registers.
Simpler hardware/control unit (hardwired control), enabling deep pipelining.
Examples: ARM, MIPS, RISC-V, PowerPC.

CISC (Complex Instruction Set Computer):

Large set of instructions, including complex, multi-cycle, variable-length instructions that can perform elaborate tasks (e.g. one instruction doing a memory load + arithmetic + store).
Many addressing modes.
Reduces program (code) size and depends less on the compiler for optimization; more of the work is done in hardware/microcode.
More complex control unit, typically microprogrammed.
Examples: Intel x86.

Summary: RISC trades instruction complexity for speed and pipeline efficiency (more instructions, but each is fast and simple); CISC trades hardware complexity for compact, powerful instructions requiring fewer instructions per program.

Part B — MCQs

2026 · Paper-I · Q1 (MCQ)

A company wants to upgrade its storage media for fastest possible data access. Which one is the best option?

A. Hard Disk Drive (HDD)
B. Optical Drive
C. Solid State Drive (SDD)
D. None of these

Answer: C

Explanation: An SSD (Solid State Drive) uses flash memory with no moving parts, giving far faster random data-access times than a mechanical HDD or an optical drive.

2026 · Paper-I · Q6 (MCQ)

How does the history of computing influence modern computer architecture?

A. By dictating hardware design
B. By shaping software development
C. By influencing both hardware and software
D. None of these

Answer: C

Explanation: Historical developments (e.g., the von Neumann architecture, transistor and IC miniaturization, early OS/compiler design) shaped both how hardware is built and how software/programming paradigms evolved, so the influence spans both areas together.

2025 · Paper-I · Q4 (MCQ)

Which of the following is commonly used for measuring the performance of supercomputers?

A. Gigahertz (GHz)
B. Teraflops (Tflops)
C. Petabyte (PB)
D. None of these

Answer: B

Explanation: Supercomputer performance is ranked by floating-point operations per second, commonly expressed in teraflops (trillions of FLOPS), not clock speed or storage capacity.

2025 · Paper-II · Q1 (MCQ)

A stack is:

A. An 8 bit register in microprocessor
B. A 16 bit register in microprocessor
C. A set of memory location in R/WM reserved for storing information temporarily during the execution of computer.
D. A 16-bit memory address stored in program counter

Answer: C

Explanation: A stack is implemented as a region of read/write memory (RAM) reserved to temporarily hold data such as return addresses and local variables during program execution; it is not a fixed-size CPU register.

2025 · Paper-II · Q2 (MCQ)

Data hazards occur when:

A. Greater performance loss
B. Pipeline changes the order of read/write access to operands
C. Some functional unit is not fully pipelined
D. Machine size is limited

Answer: B

Explanation: A data hazard arises in a pipeline when instruction overlap changes the normal order of reading/writing operands, so an instruction reads a value before a preceding instruction has written the correct/updated value.

2025 · Paper-II · Q3 (MCQ)

If computer A executes a program in 10 seconds & Computer B runs same in 15 seconds, how much faster is computer A than B?

A. 5.1 times
B. 1.4 times
C. 1 time
D. 1.5 times

Answer: D

Explanation: Speedup = time(B)/time(A) = 15/10 = 1.5, so computer A is 1.5 times faster than computer B.

2025 · Paper-II · Q4 (MCQ)

Processor having Clock cycle of 0.25ns will have clock rate of:

A. 2 GHz
B. 3 GHz
C. 4 GHz
D. 8 GHz

Answer: C

Explanation: Clock rate = 1 / clock cycle time = 1 / 0.25ns = 4 x 10^9 Hz = 4 GHz.

2024 · Paper-II · Q1 (MCQ)

Which of the following are computer architectures different from conventional von Neumann architecture?

A. MIT architecture
B. Harvard architecture
C. Turing architecture
D. None of these

Answer: B

Explanation: Harvard architecture uses physically separate storage and buses for instructions and data, unlike the von Neumann architecture's single shared memory/bus for both; 'MIT architecture' and 'Turing architecture' are not standard named computer architectures.

2024 · Paper-II · Q10 (MCQ)

In the RISC architecture, the _____ is updated whenever a function is called:

A. Frame pointer and Return address register
B. Stack pointer
C. Both (A) & (B)
D. None of these

Answer: B

Explanation: In RISC calling conventions, the stack pointer is always adjusted on every function call (to allocate a new stack frame), whereas a dedicated frame pointer or a separate return-address register is not universally used in all RISC ISAs, making the stack pointer the consistently updated register.